- 专利标题: TRIPLE-WELL CMOS DEVICES WITH INCREASED LATCH-UP IMMUNITY AND METHODS OF FABRICATING SAME
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申请号: US11683454申请日: 2007-03-08
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公开(公告)号: US20070178639A1公开(公告)日: 2007-08-02
- 发明人: Delbert Cecchi , Toshiharu Furukawa , Jack Mandelman
- 申请人: Delbert Cecchi , Toshiharu Furukawa , Jack Mandelman
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238
摘要:
A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.