公开(公告)号：US20070178639A1

公开(公告)日：2007-08-02

申请号：US11683454

申请日：2007-03-08

申请人： Delbert Cecchi ,  Toshiharu Furukawa ,  Jack Mandelman

发明人： Delbert Cecchi ,  Toshiharu Furukawa ,  Jack Mandelman

IPC分类号： H01L21/8238

CPC分类号： H01L27/0921 ,  H01L27/0928 ,  H01L29/1087 ,  H01L29/7833

摘要： A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.

公开(公告)号：US20070170516A1

公开(公告)日：2007-07-26

申请号：US11340344

申请日：2006-01-26

申请人： Delbert Cecchi ,  Toshiharu Furukawa ,  Jack Mandelman

发明人： Delbert Cecchi ,  Toshiharu Furukawa ,  Jack Mandelman

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L27/0921 ,  H01L27/0928 ,  H01L29/1087 ,  H01L29/7833

摘要： A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.

摘要翻译： 具有减小的闩锁磁化率的三阱CMOS结构和制造该结构的方法。 该方法包括在P阱下形成具有低电阻的掩埋P型掺杂层和形成CMOS晶体管的N阱，并在P阱中形成的掩埋N型掺杂层中形成间隙， 在与P阱的接触下对齐的间隙。 埋入的P型掺杂层和掩埋N型掺杂层中的间隙允许在CMOS晶体管的寄生双极晶体管周围的低电阻空穴电流路径。

公开(公告)号：US20080048683A1

公开(公告)日：2008-02-28

申请号：US11874280

申请日：2007-10-18

申请人： Delbert Cecchi

发明人： Delbert Cecchi

IPC分类号： G01R31/26

CPC分类号： G01R31/2853

摘要： A method and apparatus are provided for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. A separate power distribution is provided for coupling a positive voltage supply rail to the N well and a ground voltage supply rail to the P well of the CMOS circuit. At least one sensor monitors current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry. A latchup event is detected responsive to a predefined increase in the monitored current flow. A switch temporarily interrupts the connection of at least one of the N well and the P well to the respective voltage supply rail when the latchup event is detected.

摘要翻译： 提供了用于检测和防止体互补金属氧化物半导体（CMOS）闭锁的方法和装置。 提供了一个单独的功率分配，用于将正电压供电导轨连接到N阱，并将接地电压电源线连接到CMOS电路的P阱。 至少一个传感器监视施加到CMOS电路的N阱和P阱中的至少一个的偏置电压中的电流。 响应于所监视的电流的预定增加来检测闭锁事件。 当检测到闭锁事件时，开关暂时中断N阱和P阱中的至少一个与相应的电源供应轨的连接。

公开(公告)号：US20050110521A1

公开(公告)日：2005-05-26

申请号：US10718219

申请日：2003-11-20

申请人： Delbert Cecchi ,  Michael Launsbach ,  Curtis Preuss ,  David Siljenberg

发明人： Delbert Cecchi ,  Michael Launsbach ,  Curtis Preuss ,  David Siljenberg

IPC分类号： G01R31/3167 ,  G01R31/317 ,  H03K19/094

CPC分类号： H03K19/09432 ,  G01R31/3167 ,  G01R31/31701

摘要： A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.

摘要翻译： 提供了双模式，模拟差分和互补金属氧化物半导体（CMOS）逻辑电路。 该电路包括用于接收差分输入信号的差分输入。 开关对耦合到差分输入。 耦合到开关对的一对负载电阻器限定用于提供差分输出信号的差分输出。 电流源耦合到开关对。 控制输入​​接收控制信号，并且耦合到控制输入的控制电路禁用电流源以响应于被激活的控制信号来选择CMOS测试模式。

公开(公告)号：US20070164774A1

公开(公告)日：2007-07-19

申请号：US11335766

申请日：2006-01-19

申请人： Delbert Cecchi

发明人： Delbert Cecchi

IPC分类号： G01R31/26

CPC分类号： G01R31/2853

摘要： A method and apparatus are provided for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. A separate power distribution is provided for coupling a positive voltage supply rail to the N well and a ground voltage supply rail to the P well of the CMOS circuit. At least one sensor monitors current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry. A latchup event is detected responsive to a predefined increase in the monitored current flow. A switch temporarily interrupts the connection of at least one of the N well and the P well to the respective voltage supply rail when the latchup event is detected.

摘要翻译： 提供了用于检测和防止体互补金属氧化物半导体（CMOS）闭锁的方法和装置。 提供了一个单独的功率分配，用于将正电压供电导轨连接到N阱，并将接地电压电源线连接到CMOS电路的P阱。 至少一个传感器监视施加到CMOS电路的N阱和P阱中的至少一个的偏置电压中的电流。 响应于所监视的电流的预定增加来检测闭锁事件。 当检测到闭锁事件时，开关暂时中断N阱和P阱中的至少一个与相应的电源供应轨的连接。