发明申请
US20070190734A1 ASYMMETRIC SOURCE/DRAIN TRANSISTOR EMPLOYING SELECTIVE EPITAXIAL GROWTH (SEG) LAYER AND METHOD OF FABRICATING SAME 有权
采用选择性外延生长(SEG)层的不对称源/漏极晶体管及其制造方法

ASYMMETRIC SOURCE/DRAIN TRANSISTOR EMPLOYING SELECTIVE EPITAXIAL GROWTH (SEG) LAYER AND METHOD OF FABRICATING SAME
摘要:
According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
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