公开(公告)号：US07534708B2

公开(公告)日：2009-05-19

申请号：US11452867

申请日：2006-06-14

申请人： Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee ,  Hyeoung-Won Seo ,  Dae-Joong Won

发明人： Dong-Hyun Kim ,  Du-Heon Song ,  Sang-Hyun Lee ,  Hyeoung-Won Seo ,  Dae-Joong Won

IPC分类号： H01L21/3205

CPC分类号： H01L29/66537 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10852 ,  H01L27/10876 ,  H01L29/1041 ,  H01L29/42376 ,  H01L29/66621

摘要： For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode. Such an extra-doped channel region prevents undesired body effect in the field effect transistor.

摘要翻译： 为了制造场效应晶体管，在半导体衬底的表面的下方形成了掺杂杂质的沟道区。 在半导体衬底中形成开口，形成超掺杂沟道区。 在开口的壁处形成栅极绝缘体，使得超掺杂沟道区在开口的底部邻接栅极绝缘体。 开口填充有栅电极。 这种超掺杂沟道区域防止场效应晶体管中的不期望的体效应。

公开(公告)号：US07491603B2

公开(公告)日：2009-02-17

申请号：US11073246

申请日：2005-03-04

申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sang-Hyun Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/1087

摘要： According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

摘要翻译： 根据本发明的一些实施例，半导体器件的晶体管在沟道部分孔中具有沟道区。 方法包括形成具有设置在半导体衬底中的沟道部分孔的晶体管的实施例。 通道部分沟槽焊盘和沟道部分层依次形成在沟道部分孔的下部。 字线绝缘层图案和字线图案依次层叠在沟道部分层上并填充设置在半导体衬底上的沟道部分孔。 沟道部分层形成为通过沟道部分孔的侧壁的一部分与半导体衬底接触，并在字线图案下形成沟道区。 防止对应于源区和漏区的电极杂质区之间的穿透。

公开(公告)号：US07393769B2

公开(公告)日：2008-07-01

申请号：US11077835

申请日：2005-03-10

申请人： Hyeoung-Won Seo ,  Ki-Nam Kim ,  Woun-Suck Yang ,  Du-Heon Song

发明人： Hyeoung-Won Seo ,  Ki-Nam Kim ,  Woun-Suck Yang ,  Du-Heon Song

IPC分类号： H01L29/40

CPC分类号： H01L27/10876 ,  H01L27/0207 ,  H01L27/10861 ,  H01L29/1083

摘要： According to some embodiments of the invention, transistors of a semiconductor device have a punchthrough protection layer, and methods of forming the same are provided. A channel-portion hole extends downward from a main surface of a semiconductor substrate. A punchthrough protection layer and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line pattern fills an upper portion of the channel-portion hole, and is formed on the semiconductor substrate. The word line pattern is formed to have a word line and a word line capping layer pattern stacked thereon, and the channel-portion layer is a channel region. The punchthrough protection layer can reduce a leakage current of a capacitor of the transistor embodied in a DRAM.

摘要翻译： 根据本发明的一些实施例，半导体器件的晶体管具有穿透保护层，并且提供了其形成方法。 沟道部分孔从半导体衬底的主表面向下延伸。 穿通保护层和沟道部分层依次形成在沟道部分孔的下部。 字线图案填充沟道部分孔的上部，并形成在半导体衬底上。 字线图案形成为具有堆叠在其上的字线和字线覆盖层图案，并且沟道部分层是沟道区域。 穿透保护层可以减少体现在DRAM中的晶体管的电容器的漏电流。

公开(公告)号：US07279774B2

公开(公告)日：2007-10-09

申请号：US10938436

申请日：2004-09-09

申请人： Hyeoung-Won Seo ,  Woun-Suck Yang ,  Du-Heon Song ,  Jae-Man Youn

发明人： Hyeoung-Won Seo ,  Woun-Suck Yang ,  Du-Heon Song ,  Jae-Man Youn

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes. Gate lines are formed to overlie and extend across the channel fins. Source/drain regions are formed at both ends of the channel fins and connected by the channel fins. Other embodiments are described and claimed.

摘要翻译： finFET器件包括具有被沟槽包围的特定区域的半导体衬底。 沟槽填充有绝缘层，并且在特定区域内形成凹陷孔，使得通道散热片由凹槽两侧的半导体衬底的凸起部分形成。 栅极线形成为覆盖并延伸穿过通道散热片。 源极/漏极区域形成在通道鳍片的两端并且通过通道散热片连接。 描述和要求保护其他实施例。

公开(公告)号：US5942450A

公开(公告)日：1999-08-24

申请号：US990148

申请日：1997-12-12

申请人： Du-Heon Song

发明人： Du-Heon Song

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/00

CPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894

摘要： A method of fabricating a semiconductor device includes the steps of sequentially forming a gate oxide layer, a gate material layer and a cap insulating layer on a semiconductor substrate, selectively etching them to form a gate, sequentially forming a plurality of material layers on the overall surface of the semiconductor substrate including the gate, etching them back to form a gate sidewall spacer out of the plurality of material layers, and selectively removing the plurality of material layers forming the gate sidewall spacer to form gate sidewall spacers having lengths different from each other, the lengths depending on a particular region of the substrate.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上依次形成栅极氧化层，栅极材料层和帽绝缘层，选择性地蚀刻它们以形成栅极，在整体上依次形成多个材料层 包括栅极的半导体衬底的表面，将其回蚀刻以在多个材料层中形成栅极侧壁间隔物，并且选择性地去除形成栅极侧壁间隔物的多个材料层，以形成具有彼此长度不同的栅极侧壁间隔物 长度取决于衬底的特定区域。

公开(公告)号：US5686331A

公开(公告)日：1997-11-11

申请号：US773086

申请日：1996-12-24

申请人： Du-Heon Song

发明人： Du-Heon Song

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8232

CPC分类号： H01L29/6653 ,  H01L21/823443 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

摘要： A fabrication method for a semiconductor device which is capable of preventing the shorting of the semiconductor device by performing an ion-implantation of an impurity after forming an insulating layer on a gate electrode, and forming sidewall spacers on the upper surface of the gate electrode and at the sides thereof includes: forming on a semiconductor substrate a pattern including a gate insulating film, a gate electrode on the gate insulating film and a disposable layer on the gate electrode; forming low concentration impurity regions in the substrate by performing an ion implantation, using the pattern as a mask; forming first sidewall spacers at the sides of the pattern; forming high concentration impurity regions in the substrate by performing an ion implantation, using the pattern and the sidewall spacers as a mask; stripping the disposable layer; forming second sidewall spacers at the sides of the first sidewall spacers and on both ends of the upper surface of the gate electrode; and forming a reaction layer of a metal and a silicon on the gate electrode and the high concentration impurity regions.

摘要翻译： 一种半导体器件的制造方法，其能够通过在栅电极上形成绝缘层之后进行杂质的离子注入来防止半导体器件的短路，并且在栅电极的上表面上形成侧壁间隔物，以及 其包括：在半导体基板上形成包括栅极绝缘膜，栅极绝缘膜上的栅电极和栅电极上的一次性层的图案; 通过使用该图案作为掩模，通过进行离子注入在基板中形成低浓度杂质区域; 在图案的侧面形成第一侧壁间隔物; 通过使用图案和侧壁间隔物作为掩模，通过进行离子注入在基板中形成高浓度杂质区域; 剥离一次性层; 在第一侧壁间隔物的侧面和栅电极的上表面的两端上形成第二侧壁间隔物; 以及在栅电极和高浓度杂质区上形成金属和硅的反应层。

公开(公告)号：US07354827B2

公开(公告)日：2008-04-08

申请号：US11100685

申请日：2005-04-06

申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sun-Joon Kim ,  Jin-Woo Lee

发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Sun-Joon Kim ,  Jin-Woo Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/10873 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7834

摘要： According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is disposed to fill the channel trench and to extend over a main surface of the semiconductor substrate. Source/drain regions having a first conductivity are disposed in the active region at both sides of the channel trench. A channel impurity region having a second conductivity is disposed beneath one of the source/drain regions to be in contact with at least a sidewall of the channel trench.

摘要翻译： 根据本发明的实施例，晶体管包括具有有源区的半导体衬底。 通道槽被设置成穿过有源区域。 栅极绝缘层覆盖沟道沟槽的内壁。 设置栅极图案以填充沟道沟槽并在半导体衬底的主表面上延伸。 具有第一导电性的源极/漏极区域设置在沟道沟槽的两侧的有源区域中。 在源极/漏极区之一下方设置具有第二导电性的沟道杂质区，以与沟道沟槽的至少一个侧壁接触。

公开(公告)号：US20080029899A1

公开(公告)日：2008-02-07

申请号：US11712504

申请日：2007-03-01

申请人： Du-heon Song ,  Ho-jin Oh ,  Tai-heui Cho ,  Joo-hyun Lee

发明人： Du-heon Song ,  Ho-jin Oh ,  Tai-heui Cho ,  Joo-hyun Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L27/105 ,  H01L27/1052

摘要： A method of fabricating a semiconductor device, including forming contact pads in a first insulating layer on a substrate, forming a second insulating layer on the first insulating layer and on the contact pads, forming bit lines on the second insulating layer, the bit lines connected to a first plurality of the contact pads by bit line contact plugs, forming expanded contact holes in the second insulating layer between the bit lines, wherein the expanded contact holes are expanded toward the bit lines, and forming contact spacers on side walls of the expanded contact holes.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上的第一绝缘层中形成接触焊盘，在第一绝缘层和接触焊盘上形成第二绝缘层，在第二绝缘层上形成位线，连接位线 通过位线接触插塞连接到第一组多个接触焊盘，在位线之间的第二绝缘层中形成扩展的接触孔，其中扩大的接触孔朝向位线膨胀，并且在膨胀的 接触孔

公开(公告)号：US07300845B2

公开(公告)日：2007-11-27

申请号：US11022056

申请日：2004-12-23

申请人： Hyeoung-Won Seo ,  Du-Heon Song ,  Dae-Joong Won ,  Sang-Hyun Lee

发明人： Hyeoung-Won Seo ,  Du-Heon Song ,  Dae-Joong Won ,  Sang-Hyun Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0727 ,  H01L29/66621 ,  H01L29/66659

摘要： The method of manufacturing a recess type MOS transistor improves a refresh characteristic. In the method, a channel impurity region is formed by ion implanting a first conductive impurity in an active region of a semiconductor substrate. Thereon, a second conductive impurity and the first conductive impurity are ion-implanted each alternately into the active region, to thus sequentially form first to third impurity regions having a dual diode structure on the channel impurity region, the second conductive impurity having conductivity opposite to the first conductive impurity. A trench is formed, and a gate insulation layer is formed in a gate region to produce a gate stack. The first conductive impurity is selectively ion-implanted in a source region, to thus form a fourth impurity region. A spacer is then formed in a sidewall of the gate stack, and the second conductive impurity is ion-implanted in the source/drain regions, to form a fifth impurity region.

摘要翻译： 制造凹型MOS晶体管的方法提高了刷新特性。 在该方法中，通过在半导体衬底的有源区中离子注入第一导电杂质形成沟道杂质区。 其次，将第二导电杂质和第一导电杂质各自离子注入到有源区中，从而顺序地在沟道杂质区上形成具有双二极管结构的第一至第三杂质区，第二导电杂质具有与 第一导电杂质。 形成沟槽，并且在栅极区域中形成栅极绝缘层以产生栅极堆叠。 选择性地将第一导电杂质离子注入源极区，从而形成第四杂质区。 然后在栅极堆叠的侧壁中形成间隔物，并且将第二导电杂质离子注入源极/漏极区域中，以形成第五杂质区域。

公开(公告)号：US07221023B2

公开(公告)日：2007-05-22

申请号：US11067410

申请日：2005-02-25

申请人： Hyeoung-Won Seo ,  Nak-Jin Son ,  Du-Heon Song ,  Jun Seo

发明人： Hyeoung-Won Seo ,  Nak-Jin Son ,  Du-Heon Song ,  Jun Seo

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/66636 ,  H01L29/78 ,  Y10S438/942

摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.

摘要翻译： 根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层 离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案 ，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。 因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。