发明申请
- 专利标题: Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors
- 专利标题(中): 集成源极/漏极应力和半导体介电层应力的半导体工艺
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申请号: US11361171申请日: 2006-02-24
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公开(公告)号: US20070202651A1公开(公告)日: 2007-08-30
- 发明人: Da Zhang , Vance Adams , Bich-Yen Nguyen , Paul Grudowski
- 申请人: Da Zhang , Vance Adams , Bich-Yen Nguyen , Paul Grudowski
- 专利权人: Freescale Semiconductor, Inc.
- 当前专利权人: Freescale Semiconductor, Inc.
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.