Apparatus and method for boosting output of a generator set
    1.
    发明授权
    Apparatus and method for boosting output of a generator set 有权
    一种用于提升发电机组输出的装置和方法

    公开(公告)号:US08643217B2

    公开(公告)日:2014-02-04

    申请号:US12674936

    申请日:2007-12-26

    IPC分类号: H02J3/00

    CPC分类号: H02P9/02 Y10T307/675

    摘要: An apparatus and method for boosting output of a generator set are provided. The output of the generator set is connected to an electrical load. The apparatus includes an energy storage unit, and a power-electronic unit. The energy storage unit uses batteries and capacitors to store electric energy. The power-electronic unit measures an electrical parameter of the output of the generator set. Based on the measured electrical parameter and a predefined criterion, the power-electronic unit determines additional energy required by the electrical load. Thereafter, the power-electronic unit supplies the additional energy to the electrical load. The additional energy is drawn from the energy storage unit.

    摘要翻译: 提供了一种用于提升发电机组的输出的装置和方法。 发电机组的输出连接到电气负载。 该装置包括能量存储单元和电力电子单元。 储能单元使用电池和电容器来储存电能。 电力电子单元测量发电机组输出的电气参数。 基于测量的电参数和预定标准,功率电子单元确定电负载所需的附加能量。 此后,电力电子单元向电负载提供额外的能量。 额外的能量从能量存储单元中抽出。

    Forming a semiconductor device having epitaxially grown source and drain regions
    3.
    发明授权
    Forming a semiconductor device having epitaxially grown source and drain regions 有权
    形成具有外延生长的源区和漏区的半导体器件

    公开(公告)号:US07795089B2

    公开(公告)日:2010-09-14

    申请号:US11680219

    申请日:2007-02-28

    IPC分类号: H01L21/8238

    摘要: A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

    摘要翻译: 在具有具有隔离区域的半导体层的半导体衬底上制造半导体器件结构。 第一栅极结构形成在半导体层的第一区域上,第二栅极结构在半导体层的第二区域之上。 在第一和第二区域上形成第一绝缘层。 第一绝缘层可以在半导体层的蚀刻期间用作掩模,并且可以选择性地去除隔离区域和侧壁间隔物。 从第一区域上去除第一绝缘层,以在第二区域上留下第一绝缘层的剩余部分。 半导体层凹入与第一栅极相邻的第一区域中以形成凹陷。 在凹部中外延生长半导体材料。 去除第一绝缘层的剩余部分。

    FAN BLADES
    4.
    发明申请
    FAN BLADES 审中-公开
    风扇叶片

    公开(公告)号:US20100150731A1

    公开(公告)日:2010-06-17

    申请号:US12635665

    申请日:2009-12-10

    申请人: Da ZHANG Yuqi CHEN

    发明人: Da ZHANG Yuqi CHEN

    IPC分类号: F04D29/30 F04D29/32

    摘要: A blade for an axial fan, including at least a front edge portion, a back edge portion, and multiple pressure balance holes. The front edge portion operates to blow air from the outside of the blade, the back edge portion operates to blow air to the outside of the blade, and the pressure balance hole is disposed on the back edge portion. The pressure balance holes are adapted to balance pressure and reduce pressure difference between the front side and the back side of the blade, eliminating backflow phenomenon caused by separation of boundary layer airflow at the back edge portion on a windward side of the blade and thus reducing power consumption and noise, and preventing dust from settling on the back edge portion on the windward side of the blade.

    摘要翻译: 一种用于轴流风扇的叶片,至少包括前边缘部分,后边缘部分和多个压力平衡孔。 前边缘部分操作以从叶片的外部吹出空气,后边缘部分操作以将空气吹向叶片的外部,并且压力平衡孔设置在后边缘部分上。 压力平衡孔适于平衡压力并减小叶片的前侧和后侧之间的压力差,消除了由于在叶片的迎风侧的后边缘部分分离边界层气流而引起的回流现象,从而减少 功率消耗和噪音,并且防止灰尘沉降在叶片的迎风侧的后边缘部分上。

    Method for Transistor Fabrication with Optimized Performance
    5.
    发明申请
    Method for Transistor Fabrication with Optimized Performance 有权
    具有优化性能的晶体管制造方法

    公开(公告)号:US20100078687A1

    公开(公告)日:2010-04-01

    申请号:US12242078

    申请日:2008-09-30

    IPC分类号: H01L21/8238 H01L29/04

    摘要: A semiconductor process and apparatus includes forming channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).

    摘要翻译: 一种半导体工艺和设备包括在NMOS沟道区中形成具有增强的空穴迁移率的<100>沟道定向CMOS晶体管(24,34),并且通过在PMOS区上沉积第一拉伸蚀刻停止层(51),减小PMOS区域中的沟道缺陷率 蚀刻所述拉伸蚀刻停止层(51)以在所述暴露的栅极侧壁上形成拉伸侧壁间隔物(62),然后在所述NMOS和PMOS栅极上沉积第二富氢压缩或中性蚀刻停止层(72) 结构(26,36)和拉伸侧壁间隔物(62)。 在其它实施例中,沉积并蚀刻第一富氢蚀刻停止层(81)以在暴露的栅极侧壁上形成侧壁间隔物(92),然后在NMOS和PMOS上沉积第二拉伸蚀刻停止层(94) 栅极结构(26,36)和侧壁间隔物(92)。

    RECEIVING DEVICE FOR A MAGNETIC RESONANCE IMAGING SYSTEM
    6.
    发明申请
    RECEIVING DEVICE FOR A MAGNETIC RESONANCE IMAGING SYSTEM 有权
    用于磁共振成像系统的接收装置

    公开(公告)号:US20090174408A1

    公开(公告)日:2009-07-09

    申请号:US12350284

    申请日:2009-01-08

    IPC分类号: G01R33/34

    摘要: A receiving device for an MRI (magnetic resonance imaging) system has multiple receiving coils. In the same imaging acceleration direction, a junction region is formed between adjacent receiving coils. An additional receiving coil is arranged on the junction region. The additional receiving coil covers at least partially a line of strong phase variation in sensitivity at the boundary of said junction region. This receiving device alleviates the problem of poor sensitivity to MRI signals in the junction region in the imaging acceleration direction, so as to improve the imaging quality in the junction region, and thus improving the overall imaging quality.

    摘要翻译: 用于MRI(磁共振成像)系统的接收装置具有多个接收线圈。 在相同的成像加速方向上,在相邻的接收线圈之间形成接合区域。 在接合区域上设置一个附加的接收线圈。 附加接收线圈至少部分地覆盖在所述接合区域的边界处的灵敏度的强相位变化的线。 该接收装置缓解了在成像加速方向上的结区域对MRI信号的敏感性差的问题,以提高接合区域的成像质量,从而提高整体成像质量。

    METHOD AND APPARATUS FOR CORRECTING DISTORTION DURING MAGNETIC RESONANCE IMAGING
    7.
    发明申请
    METHOD AND APPARATUS FOR CORRECTING DISTORTION DURING MAGNETIC RESONANCE IMAGING 有权
    用于校正磁共振成像期间的失真的方法和装置

    公开(公告)号:US20090169084A1

    公开(公告)日:2009-07-02

    申请号:US12344922

    申请日:2008-12-29

    IPC分类号: G06K9/00 G06K9/40

    摘要: In a method and apparatus for correcting distortion during magnetic resonance imaging k space data in a number of readout encoding directions, wherein the sampling points on the phase encoding lines are concentrated in low frequency regions and their number is less than that of full sampling points. A view angle tilting compensation gradient is superimposed on the axis of a layer selection gradient. The k space data acquired from the number of directions are then combined. Due to the fact that the superimposition of the view angle tilting compensation gradient on the axis of the slice selection gradient can effectively correct geometric distortions, and at the same time the resolution in phase encoding lines is relatively high, low resolution contents are provided only in readout encoding directions, so the degree of blurring in the final image is substantially reduced. Furthermore, by acquiring the k space data in a number of readout directions the sensitivity to motion artifacts can effectively be reduced. Not only can correction of the geometric distortion be performed during magnetic resonance imaging, but the degree of blurring and motion artifacts in the final image.

    摘要翻译: 在用于校正多个读出编码方向的磁共振成像k空间数据中的失真的方法和装置中,其中相位编码线上的采样点集中在低频区域中,并且它们的数量小于全采样点的数目。 视角倾斜补偿梯度叠加在层选择梯度的轴上。 然后组合从多个方向获得的k个空间数据。 由于视角倾斜补偿梯度在切片选择梯度的轴上的叠加可以有效地校正几何失真,同时相位编码线中的分辨率相对较高,所以仅在 读取编码方向,因此最终图像中的模糊程度显着降低。 此外,通过在多个读出方向上获取k空间数据,可以有效地降低对运动伪影的敏感度。 不仅可以在磁共振成像期间执行几何失真的校正,而且可以在最终图像中进行模糊和运动伪影的程度。

    Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors
    8.
    发明授权
    Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors 失效
    集成源极/漏极应力和半导体介电层应力的半导体工艺

    公开(公告)号:US07538002B2

    公开(公告)日:2009-05-26

    申请号:US11361171

    申请日:2006-02-24

    IPC分类号: H01L21/336

    摘要: A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

    摘要翻译: 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构,形成覆盖晶体管区域的栅极结构,去除源极/漏极区域以形成源极/漏极凹部,去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上,使得ILD应力源与源极/漏极结构的侧壁相邻,从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅,并且源极/漏极结构优选为硅锗或硅碳。

    Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor
    9.
    发明授权
    Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor 失效
    使用蚀刻停止层的半导体制造工艺来优化源极/漏极应力源的形成

    公开(公告)号:US07494856B2

    公开(公告)日:2009-02-24

    申请号:US11393340

    申请日:2006-03-30

    IPC分类号: H01L21/336

    摘要: A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.

    摘要翻译: 半导体制造工艺包括形成覆盖掩埋氧化物(BOX)层和覆盖ESL的有源半导体层的蚀刻停止层(ESL)。 形成覆盖有源半导体层的栅电极。 蚀刻有源半导体层的源极/漏极区域以露出ESL。 源极/漏极应力源在ESL上形成,其源极/漏极应力应变应变晶体管沟道。 形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。 优选地,有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。 可以使用加热至约75℃温度的NH 4 OH:H 2溶液进行湿式蚀刻来蚀刻源极/漏极区域。 ESL可以是具有第一百分比的锗的硅锗。 源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗,并且它们可以是N型晶体管的硅碳。

    ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR FIN AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE
    10.
    发明申请
    ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR FIN AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
    包括半导体器件的电子器件和用于形成电子器件的工艺

    公开(公告)号:US20080296620A1

    公开(公告)日:2008-12-04

    申请号:US12174357

    申请日:2008-07-16

    IPC分类号: H01L29/778 H01L21/336

    摘要: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

    摘要翻译: 电子器件可以包括覆盖绝缘层的半导体鳍片。 电子器件还可以包括覆盖半导体鳍片的半导体层。 半导体层可以具有彼此间隔开的第一部分和第二部分。 在一个方面,电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。 电子器件还可以包括覆盖半导体层的金属 - 半导体层。 在另一方面,半导体层可以邻接半导体鳍并包括掺杂剂。 在另一方面,形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。 在另一方面,一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。