The present invention provides a digital circuit comprising an inverter gate delay line and a delay adjustment circuit. The inverter gate delay line comprises a series of a plurality of inverter gates that receives a serial data. The delay adjustment circuit comprises a replica inverter gate delay line comprising a series of a plurality of inverter gates and being configured to receive a first signal, a plurality of flip flops, each one of the plurality of flip flops electrically connected to the corresponding inverter gates of the replica inverter gate delay line, wherein the plurality of flip flops store binary information and the first flip flop of the plurality of flip flops receives a second signal which has a time delay with respect to the first signal, an encoder being electrically connected to the plurality of flip flops and determining the numbers of the needed inverter gates of the inverter gate delay line based on the binary information stored in the plurality of flip flops, and a delay selector being electrically connected to the encoder and the plurality of inverter gates of the inverter gate delay line and causing the serial data delayed by the inverter gates of the inverter gate delay line, wherein the numbers of the inverter gates of the inverter gate delay line are determined by an output of the encoder.