发明申请
- 专利标题： Stratified underfill in an IC package
- 专利标题（中）： IC封装中分层的底部填充物
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申请号： US11393050申请日： 2006-03-29
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公开(公告)号： US20070238220A1公开(公告)日： 2007-10-11
- 发明人: Mirng-Ji Lii , Szu Lu , Tjandra Karta , Chien-Hsiun Lee
- 申请人： Mirng-Ji Lii , Szu Lu , Tjandra Karta , Chien-Hsiun Lee
- 主分类号： H01L21/00
- IPC分类号： H01L21/00
摘要：
A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.
公开/授权文献
- US07656042B2 Stratified underfill in an IC package 公开/授权日：2010-02-02
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