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公开(公告)号:US20070246821A1
公开(公告)日:2007-10-25
申请号:US11408155
申请日:2006-04-20
申请人: Szu Lu , Clinton Chao , Tjandra Karta , Jerry Tzou , Kuo-Chin Chang
发明人: Szu Lu , Clinton Chao , Tjandra Karta , Jerry Tzou , Kuo-Chin Chang
CPC分类号: H01L21/563 , H01L21/6835 , H01L23/055 , H01L23/3121 , H01L23/36 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48145 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/12044 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/157 , H01L2924/181 , H01L2924/351 , H01L2224/81 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要: A semiconductor package assembly having reduced stresses and a method for forming the same are provided. The method includes providing a package substrate comprising a base material, forming an interconnect structure overlying the package substrate, attaching at least one chip to a first surface of the package substrate, thinning the package substrate from a second surface opposite the first surface wherein the semiconductor material is substantially removed, and attaching ball grid array (BGA) balls to deep vias exposed on the second surface of the package substrate after thinning the package substrate.
摘要翻译: 提供了具有减小的应力的半导体封装组件及其形成方法。 该方法包括提供包括基材的封装衬底,形成覆盖封装衬底的互连结构,将至少一个芯片附接到封装衬底的第一表面,使封装衬底从与第一表面相反的第二表面变薄,其中半导体 基本上去除了材料,并且在将封装衬底细化之后,将球栅阵列(BGA)球附着到在封装衬底的第二表面上暴露的深通孔。
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公开(公告)号:US20070238220A1
公开(公告)日:2007-10-11
申请号:US11393050
申请日:2006-03-29
申请人: Mirng-Ji Lii , Szu Lu , Tjandra Karta , Chien-Hsiun Lee
发明人: Mirng-Ji Lii , Szu Lu , Tjandra Karta , Chien-Hsiun Lee
IPC分类号: H01L21/00
CPC分类号: H01L21/563 , H01L23/295 , H01L23/3128 , H01L2224/05022 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01019 , H01L2924/01063 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/01327 , H01L2924/15311 , H01L2924/00 , H01L2924/00014
摘要: A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.
摘要翻译: 一种方法包括使用位于管芯和封装衬底或印刷电路板之间的多个焊料凸块将具有至少一个低k电介质层的集成电路管芯连接到封装衬底或印刷电路板。 低k电介质层的介电常数约为3.0或更小。 焊锡凸块的铅浓度约为5%以下。 在模具和封装衬底或印刷电路板之间形成分层的底部填充物。
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公开(公告)号:US5331200A
公开(公告)日:1994-07-19
申请号:US954183
申请日:1992-09-30
申请人: Boon C. Teo , Tjandra Karta , Siu W. Low
发明人: Boon C. Teo , Tjandra Karta , Siu W. Low
CPC分类号: H01L23/49551 , H01L23/4951 , H01L23/49534 , H01L23/49537 , H01L23/50 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/14 , H01L2924/181
摘要: A multi-level lead frame configuration (114) for an integrated circuit chip (116) comprises a main lead frame (115) having a plurality of lead frame bond fingers (122 and 124) that directly connect to a plurality of bond pads (126) on the integrated circuit chip (116). Associated with the main lead frame (115) is a bus bar lead frame (128 and 130) having a plurality of bus bar lead fingers (118 and 120) that directly connect to a second plurality of inner bond pads (126) on the integrated circuit chip (116). The bus bar bond fingers (118 and 120) associate with the main lead frame (115) and main lead frame bond fingers (122 and 124) to permit a lead-on-chip configuration of the main lead frame and the bus bar lead frame.
摘要翻译: 一种用于集成电路芯片(116)的多级引线框架(114)包括一个主引线框架(115),它具有直接连接到多个接合焊盘(126)的多个引线框结合指(122和124) )在集成电路芯片(116)上。 与主引线框架(115)相关联的是具有多个汇流条引线指(118和120)的汇流条引线框架(128和130),该多个汇流条引线指(118和120)直接连接到集成的第一多个内焊盘 电路芯片(116)。 汇流条接合指状物(118和120)与主引线框架(115)和主引线框架结合指状物(122和124)相关联,以允许主引线框架和汇流条引线框架的引线上芯片配置 。
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