发明申请
US20070242519A1 Method of erasing data in non-volatile semiconductor memory device while suppressing variation 有权
在抑制变化的同时擦除非易失性半导体存储器件中的数据的方法

  • 专利标题: Method of erasing data in non-volatile semiconductor memory device while suppressing variation
  • 专利标题(中): 在抑制变化的同时擦除非易失性半导体存储器件中的数据的方法
  • 申请号: US11812704
    申请日: 2007-06-21
  • 公开(公告)号: US20070242519A1
    公开(公告)日: 2007-10-18
  • 发明人: Takashi ItoHidenori Mitani
  • 申请人: Takashi ItoHidenori Mitani
  • 申请人地址: JP Tokyo
  • 专利权人: Renesas Technology Corp.
  • 当前专利权人: Renesas Technology Corp.
  • 当前专利权人地址: JP Tokyo
  • 优先权: JP2005-012645 20050120
  • 主分类号: G11C16/34
  • IPC分类号: G11C16/34
Method of erasing data in non-volatile semiconductor memory device while suppressing variation
摘要:
According to a method of erasing data in a non-volatile semiconductor memory device, block-round type overerase verify is performed. Specifically, overerase verify and write back are performed sequentially from a first address to a last address. That is, even when a write back pulse is applied after a certain address is selected and verify is performed, address increment from one address to another is performed, regardless of whether verify has been performed or not. Therefore, it is not that the same address is cumulatively rewritten, but write back to a memory cell corresponding to a defective address is sequentially and gradually performed. Accordingly, as write to a memory cell in an overerased state can evenly be performed, influence by off-leakage is suppressed, and a memory cell having threshold voltage distribution with less variation can be implemented.
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