A SiP includes a logic chip and a memory chip. The memory chip includes a memory circuit to be tested, and the logic chip includes an internal logic circuit and a test processor electrically connected therewith. The test processor is connected with an access terminal of the memory circuit and supplies a test signal input from an external terminal to the access terminal to thereby test the memory circuit. The test processor includes a high-speed test control circuit to adjust signal delay and supplies a test signal from the external terminal to the access terminal through the high-speed test control circuit when performing high-speed test at an actual operation speed.