- 专利标题: Semiconductor memory device and semiconductor integrated circuit device
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申请号: US11812596申请日: 2007-06-20
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公开(公告)号: US20070247952A1公开(公告)日: 2007-10-25
- 发明人: Noriyoshi Watanabe , Noriaki Maeda , Masanao Yamaoka , Yoshihiro Shinozaki
- 申请人: Noriyoshi Watanabe , Noriaki Maeda , Masanao Yamaoka , Yoshihiro Shinozaki
- 优先权: JPJP2003-304013 20030828
- 主分类号: G11C5/14
- IPC分类号: G11C5/14
摘要:
A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
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