发明申请
- 专利标题: MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
- 专利标题(中): 存储器控制器,具有需要的信号输出
-
申请号: US11768107申请日: 2007-06-25
-
公开(公告)号: US20070247961A1公开(公告)日: 2007-10-25
- 发明人: Ian Shaeffer , Bret Stott , Benedict Lau
- 申请人: Ian Shaeffer , Bret Stott , Benedict Lau
- 主分类号: G11C8/00
- IPC分类号: G11C8/00
摘要:
A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
公开/授权文献
- US07558150B2 Memory controller with staggered request signal output 公开/授权日:2009-07-07