公开(公告)号：US10445226B2

公开(公告)日：2019-10-15

申请号：US13814917

申请日：2011-08-04

申请人： Ian Shaeffer ,  Brent S. Haukness

发明人： Ian Shaeffer ,  Brent S. Haukness

IPC分类号： G06F12/00 ,  G11C16/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

摘要： A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.

公开(公告)号：US09665507B2

公开(公告)日：2017-05-30

申请号：US13105798

申请日：2011-05-11

申请人： Ian Shaeffer ,  Thomas J. Giovannini

发明人： Ian Shaeffer ,  Thomas J. Giovannini

IPC分类号： G06F13/16 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22

CPC分类号： G06F13/1689 ,  G06F12/00 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/2254

摘要： Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

公开(公告)号：US09263103B2

公开(公告)日：2016-02-16

申请号：US12049928

申请日：2008-03-17

申请人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

发明人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC分类号： G06F12/00 ,  G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409

CPC分类号： G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

摘要翻译： 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。 在该系统的变型中，存储器芯片上的相位检测器被配置为从存储器控制器接收包括时钟信号，标记信号和数据选通信号的信号，其中标记信号包括标记特定时钟的脉冲 在时钟信号周期。 在该变型中，相位检测器被配置为使用标记信号来在时钟信号中画出特定时钟周期，并且使用数据选通信号来捕获窗口化的时钟信号，从而产生返回到 内存控制器便于校准时序关系。

公开(公告)号：US20150255144A1

公开(公告)日：2015-09-10

申请号：US14698755

申请日：2015-04-28

申请人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

发明人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC分类号： G11C11/4076 ,  G11C11/409

CPC分类号： G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

摘要翻译： 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。

公开(公告)号：US09098281B2

公开(公告)日：2015-08-04

申请号：US13980368

申请日：2012-03-08

申请人： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

发明人： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC分类号： G06F1/04 ,  G06F1/32 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076

CPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

摘要： An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

摘要翻译： 集成电路包括具有控制定时域和数据定时域的物理层接口，以及响应于第一事件而在功率节省模式改变期间实现控制定时域的电路，并且响应于数据定时域 到第二个事件。 控制定时域可以包括耦合到命令和地址路径的接口电路，并且数据定时域可以包括耦合到数据路径的接口电路。

公开(公告)号：US20130339775A1

公开(公告)日：2013-12-19

申请号：US13980368

申请日：2012-03-08

申请人： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

发明人： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC分类号： G06F1/32 ,  G06F1/04

CPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

摘要： An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US08539152B2

公开(公告)日：2013-09-17

申请号：US13149682

申请日：2011-05-31

申请人： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

发明人： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC分类号： G06F12/00

CPC分类号： G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US20130227183A1

公开(公告)日：2013-08-29

申请号：US13883542

申请日：2011-11-07

申请人： Ian Shaeffer ,  Frederick A. Ware

发明人： Ian Shaeffer ,  Frederick A. Ware

IPC分类号： G06F13/16

CPC分类号： G06F12/1458 ,  G06F12/023 ,  G06F13/16 ,  G06F13/1657 ,  G06F13/1684 ,  G06F13/1694 ,  G06F2212/1044 ,  G06F2212/1052

摘要： A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

摘要翻译： 一种多级存储器系统，其中在存储器控制器和一级存储器之间执行校准操作，同时数据在控制器和其他等级的存储器之间传送。 存储器控制器执行校准操作，其校准与存储器控制器和存储器的第一等级中的存储器件之间经由第一数据总线的数据传输有关的参数。 当控制器执行校准操作时，控制器还经由第二数据总线将存储器件中的数据与第二等级的存储器传送数据。

公开(公告)号：US08484407B2

公开(公告)日：2013-07-09

申请号：US12809039

申请日：2008-12-23

申请人： Brent Haukness ,  Ian Shaeffer

发明人： Brent Haukness ,  Ian Shaeffer

IPC分类号： G06F12/00

CPC分类号： G11C16/32 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C16/04 ,  G11C16/107 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/4402

摘要： This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly. A mechanism is also provided for recalibrating memory previously marked. By minimizing variability, flash memory can be applied to a broader range of designs and potentially to a broader set of main memory applications.

摘要翻译： 本公开提供了一种准确地确定与诸如设备，块或页面之类的闪速存储器细分有关的预期交易时间的方法。 通过执行测试事务来对每个这样的单元的每个位进行编程，可以预先确定每个单元的最大预期编程时间并用于调度目的。 例如，在简单的实现中，可以识别相对精确的经验测量的时间限制并用于有效地管理和调度闪速存储器事务，而不等待最终解决写入非响应页面的尝试。 本公开还提供经验测量的最大闪存交易时间的其他用途，包括经由多个存储器模式和优先存储器; 例如，如果需要高性能模式，则可以容忍闪速存储器交易时间的低变化，并且可以相对快速地标记不满足这些原理的单元。 还提供了一种用于重新校准之前标记的存储器的机制。 通过最小化可变性，闪存可以应用于更广泛的设计，并可能应用于更广泛的主存储器应用。

公开(公告)号：US20130173871A1

公开(公告)日：2013-07-04

申请号：US13627870

申请日：2012-09-26

申请人： Ian Shaeffer

发明人： Ian Shaeffer

IPC分类号： G06F12/00

CPC分类号： G11C8/16 ,  G06F12/00 ,  G06F13/4018 ,  G06F13/4243 ,  G11C8/06

摘要： Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

摘要翻译： 描述的是使用固定宽度内存模块支持动态点对点可扩展性的内存模块。 存储器模块包括数据宽度转换器，其允许模块改变其外部存储器接口的有效宽度，而不改变在转换器和相关联的固定宽度管芯之间延伸的内部存储器接口的宽度。 数据宽度转换器使用数据掩码信号来选择性地阻止对物理地址子集的存储器访问。 该数据屏蔽将物理地址位置划分为物理地址位置的两个或更多个时间子集，从而有效地增加给定模块中唯一可寻址位置的数量。 以写入顺序读取时间地址可能会引入不期望的读取延迟。 一些实施例重新排序读取数据以减少该等待时间。