发明申请
- 专利标题: PATTERN ARRANGEMENT METHOD OF SEMICONDUCTOR DEVICE
- 专利标题(中): 半导体器件的图案布置方法
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申请号: US11674594申请日: 2007-02-13
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公开(公告)号: US20070264584A1公开(公告)日: 2007-11-15
- 发明人: In-Sung KIM , Sung-Soo SUH , Suk-Joo LEE , Sung-Hwan BYUN , Sang-Wook KIM
- 申请人: In-Sung KIM , Sung-Soo SUH , Suk-Joo LEE , Sung-Hwan BYUN , Sang-Wook KIM
- 申请人地址: JP Gyeonggi-do
- 专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址: JP Gyeonggi-do
- 优先权: KR2006-13856 20060213
- 主分类号: G03F1/00
- IPC分类号: G03F1/00
摘要:
A pattern arrangement method of a semiconductor device is provided. In the pattern arrangement method, patterns are classified according to effective pitches and critical dimensions, and pattern dispersion is predicted according to the effective pitches and the critical dimensions by using a statistical analysis of process parameters. Two-dimensional coordinates of the effective pitches and the critical dimensions are constructed, and a dispersion map is made by arranging the predicted pattern dispersion on the corresponding coordinates. By arranging design patterns within a tolerance region of the dispersion map, the patterns satisfying the dispersion tolerance according to the significance of the layer and the design requirements can be arranged.
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