公开(公告)号：US20070264584A1

公开(公告)日：2007-11-15

申请号：US11674594

申请日：2007-02-13

申请人： In-Sung KIM ,  Sung-Soo SUH ,  Suk-Joo LEE ,  Sung-Hwan BYUN ,  Sang-Wook KIM

发明人： In-Sung KIM ,  Sung-Soo SUH ,  Suk-Joo LEE ,  Sung-Hwan BYUN ,  Sang-Wook KIM

IPC分类号： G03F1/00

CPC分类号： G03F1/36

摘要： A pattern arrangement method of a semiconductor device is provided. In the pattern arrangement method, patterns are classified according to effective pitches and critical dimensions, and pattern dispersion is predicted according to the effective pitches and the critical dimensions by using a statistical analysis of process parameters. Two-dimensional coordinates of the effective pitches and the critical dimensions are constructed, and a dispersion map is made by arranging the predicted pattern dispersion on the corresponding coordinates. By arranging design patterns within a tolerance region of the dispersion map, the patterns satisfying the dispersion tolerance according to the significance of the layer and the design requirements can be arranged.

摘要翻译： 提供了一种半导体器件的图案布置方法。 在图案布置方法中，根据有效间距和临界尺寸对图案进行分类，通过使用工艺参数的统计分析，根据有效间距和关键尺寸预测图案色散。 构建有效间距和临界尺寸的二维坐标，并通过将预测图案色散布置在相应的坐标上来进行色散图。 通过在色散图的公差区域内布置设计图案，可以布置根据层的重要性和设计要求满足色散公差的图案。