With the development of microelectronic industry, we can integrate more and more transistors in a single chip. According to Moore's law, the number of transistors can double in 18 months. Therefore, our target is how to convert the number of transistors to the performance of microprocessors as well as DSPs. In fact, three common available architectures namely superscalar, VLIW, and chip-multiprocessor do not fulfill this requirement well. Hence, in this paper, we propose a totally new architecture which is absolutely scalable. That means the design task is very easy (we design only one processing element), we exploit the whole potential of the number of transistors (we replicate the processing element as many as possible), and the performance of the chip is extremely high (hundreds or thousands processing elements can run simultaneously). We call this new architecture is “Network on Chip Dataflow Architecture” because we combine the idea of dataflow computers from the 80s with state of the art Network on Chip to create a very powerful processing architecture.