发明申请
- 专利标题: METHOD AND APPARATUS FOR MEASURING THE DUTY CYCLE OF A DIGITAL SIGNAL
- 专利标题(中): 用于测量数字信号占空比的方法和装置
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申请号: US11383570申请日: 2006-05-16
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公开(公告)号: US20070271051A1公开(公告)日: 2007-11-22
- 发明人: David Boerstler , Eskinder Hailu , Jieming Qi
- 申请人: David Boerstler , Eskinder Hailu , Jieming Qi
- 申请人地址: US TX Austin
- 专利权人: IBM Corporation
- 当前专利权人: IBM Corporation
- 当前专利权人地址: US TX Austin
- 主分类号: G01R29/02
- IPC分类号: G01R29/02 ; G01R25/00
摘要:
The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.