公开(公告)号：US20070236266A1

公开(公告)日：2007-10-11

申请号：US11278842

申请日：2006-04-06

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： H03K5/1534 ,  H03K5/156 ,  H03K2005/00293

摘要： An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells utilized in the circuit arrangement described in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 (hereafter referred to as the '090 application). The elimination of these delay cells is made possible in one illustrative embodiment by replacing an OR gate in the circuit configuration of the '090 application with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.

摘要翻译： 提供了一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法。 说明性实施例的装置和方法使用被配置为消除在共同转让和共同未决的美国专利申请Ser中描述的电路装置中使用的大多数延迟单元的电路来执行这种提取。 第11 / 109,090号（以下简称“090”）。 在一个说明性实施例中，通过用'边缘触发的可重新设定的锁存器'替换'090应用的电路配置中的或门，可以消除这些延迟单元。 利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

公开(公告)号：US20070126475A1

公开(公告)日：2007-06-07

申请号：US11466542

申请日：2006-08-23

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K19/173

CPC分类号： G01R31/2632

摘要： A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.

摘要翻译： 提供了一种半自动提取二极管理想因子的方法，装置和计算机程序。 传统上，二极管的电流/电压曲线为理想因素外推提供了基础，必须用手来确定。 通过采用与绝对温度（PTAT）发生器成比例的热电压与提取机制，理想因子可以半自动提取。 因此，可以采用可靠，快速和便宜的装置来改善理想因素的测量。

公开(公告)号：US20070079197A1

公开(公告)日：2007-04-05

申请号：US11242677

申请日：2005-10-04

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R31/28

CPC分类号： H03K5/1565 ,  G01R31/31727 ,  G01R31/3187

摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. Results of a built-in self test, i.e. pass or fail, of an array are provided to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.

摘要翻译： 提供一种用于自动校准占空比电路以实现最大性能的装置和方法。 提供了自动校准每个芯片的占空比校正（DCC）电路设置的芯片级内置电路。 该芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。 向DCC电路控制器提供阵列的内置自检，即通过或失败的结果。 如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。 如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

公开(公告)号：US20060232310A1

公开(公告)日：2006-10-19

申请号：US11109090

申请日：2005-04-19

申请人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： H03K5/156 ,  G01R31/31708 ,  G01R31/31725 ,  H03K5/05 ,  H03K5/26

摘要： The present invention provides for a method for characterization of pulse-width limiter outputs. A known clock signal is received. A pulse width of the received known clock signal is limited through a first pulse-width limiter to generate a first intermediate signal. The first intermediate signal is delayed by a known amount to generate a first delayed signal. The first intermediate signal is inverted to generate a first inverted signal. A pulse width of the first inverted signal is limited through a second pulse-width limiter to generate a second intermediate signal. The second intermediate signal is delayed by a known amount to generate a second delayed signal. A logic OR operation is performed on the first delayed signal and the second delayed signal to generate a clock out signal.

摘要翻译： 本发明提供了用于表征脉冲宽度限制器输出的方法。 接收已知的时钟信号。 所接收的已知时钟信号的脉冲宽度通过第一脉冲宽度限制器来限制，以产生第一中间信号。 第一中间信号被延迟已知的量以产生第一延迟信号。 第一中间信号被反相以产生第一反相信号。 通过第二脉冲宽度限幅器限制第一反相信号的脉冲宽度以产生第二中间信号。 第二中间信号被延迟已知的量以产生第二延迟信号。 对第一延迟信号和第二延迟信号执行逻辑或运算以产生时钟输出信号。

公开(公告)号：US20050261866A1

公开(公告)日：2005-11-24

申请号：US10850401

申请日：2004-05-20

申请人： David Boerstler ,  Hiroki Kihara ,  Robert Putney ,  Daniel Stasiak ,  Michael Wang

发明人： David Boerstler ,  Hiroki Kihara ,  Robert Putney ,  Daniel Stasiak ,  Michael Wang

IPC分类号： G01R31/26 ,  G01K7/01 ,  G01R31/28 ,  G06F15/00

CPC分类号： G01K7/01

摘要： The present invention provides for determining a temperature in a chip. A voltage across a thermal diode is generated. It is then determined whether the voltage across the first thermal diode exceeds a threshold value. The voltage is correlated with a range of values. The determination of whether the voltage across the thermal diode exceeds the threshold value is correlated with the correlation of the voltage with a range of values. Through the use of voltage level sensors, the use of C4 input/output pins are avoided.

摘要翻译： 本发明提供用于确定芯片中的温度。 产生热二极管两端的电压。 然后确定第一热二极管两端的电压是否超过阈值。 电压与值的范围相关。 确定热二极管上的电压是否超过阈值与电压与一定范围的值的相关性相关。 通过使用电压电平传感器，可以避免使用C4输入/输出引脚。

公开(公告)号：US20050248376A1

公开(公告)日：2005-11-10

申请号：US10840562

申请日：2004-05-06

申请人： David Boerstler ,  Eskinder Hailu

发明人： David Boerstler ,  Eskinder Hailu

IPC分类号： H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/093

CPC分类号： H03L7/093 ,  H03L7/0891

摘要： The present invention provides for a low pass filter. A first capacitor, has a first associated leakage current. A second capacitor has a specified capacitance that is a fraction of the capacitance of the first capacitor, the second capacitor further having a second associated leakage current. A voltage follower circuit is coupled to the output of the first and second capacitor. First and second current sources are coupled to the voltage follower circuit. A bias current source is coupled the first current source. A current mirror is coupled to the second current source, and the current mirror is further coupled to at least the anode of the first capacitor, thereby generating replacement current of a capacitor within a low-pass filter.

摘要翻译： 本发明提供一种低通滤波器。 第一电容器具有第一相关泄漏电流。 第二电容器具有指定电容，其是第一电容器的电容的一部分，第二电容器还具有第二相关联的漏电流。 电压跟随器电路耦合到第一和第二电容器的输出。 第一和第二电流源耦合到电压跟随器电路。 偏置电流源耦合第一电流源。 电流镜耦合到第二电流源，并且电流镜还被耦合到至少第一电容器的阳极，从而产生低通滤波器内的电容器的替换电流。

公开(公告)号：US20050018799A1

公开(公告)日：2005-01-27

申请号：US10439039

申请日：2003-05-15

申请人： David Boerstler ,  Chulwoo Kim ,  Stephen Weitzel

发明人： David Boerstler ,  Chulwoo Kim ,  Stephen Weitzel

IPC分类号： H04L7/00 ,  H04L7/02

CPC分类号： H04L7/0012

摘要： The present invention discloses, in one aspect, a synchronizing circuit for synchronizing transmitted data. In one embodiment, the synchronization technique comprises a subsystem configured to compare positive and negative transitions of a core clock signal with positive and negative transitions of a source clock signal to determine a relationship between the transitions of the core clock signal and positions of the negative transitions of the source clock signal. The synchronization circuit also comprises logic circuitry coupled to the subsystem and configured to generate a final sampling signal based on the relationship. In addition, the synchronization circuit comprises a data sampler coupled to the logic circuitry and configured to sample a source data signal synchronized with the source clock signal using the final sampling signal, and to generate a core data signal synchronized with the core clock signal based on the sampling. Also disclosed is a method of synchronizing a data stream, and a data transfer assembly incorporating the synchronization circuit and the method.

摘要翻译： 本发明在一个方面公开了一种用于同步发送数据的同步电路。 在一个实施例中，同步技术包括子系统，被配置为将核心时钟信号的正和负转换与源时钟信号的正和负转换进行比较，以确定核心时钟信号的转变与负转换位置之间的关系 的源时钟信号。 同步电路还包括耦合到子系统并被配置为基于该关系产生最终采样信号的逻辑电路。 另外，同步电路包括耦合到逻辑电路并被配置为使用最终采样信号对与源时钟信号同步的源数据信号进行采样的数据采样器，并且产生与基于时钟信号同步的核心数据信号 抽样。 还公开了一种同步数据流的方法，以及包含同步电路和方法的数据传输组件。

公开(公告)号：US20050010885A1

公开(公告)日：2005-01-13

申请号：US10616881

申请日：2003-07-10

申请人： Anthony Aipperspach ,  David Boerstler ,  Dieter Wendel

发明人： Anthony Aipperspach ,  David Boerstler ,  Dieter Wendel

IPC分类号： G06F9/45 ,  G06F17/50 ,  H03K5/156 ,  H03L7/06

CPC分类号： H03K5/1565 ,  H03L7/06

摘要： A method and an apparatus are provided for limiting a pulse width in a chip clock design of a circuit. The circuit receives a clock signal having a clock pulse width. The clock pulse width of the clock signal is detected. It is determined whether the clock pulse width is larger than a maximum clock pulse width. Upon a determination that the clock pulse width is larger than a maximum clock pulse width, the clock pulse width of the clock signal is limited.

摘要翻译： 提供了一种用于限制电路的芯片时钟设计中的脉冲宽度的方法和装置。 该电路接收具有时钟脉冲宽度的时钟信号。 检测时钟信号的时钟脉冲宽度。 确定时钟脉冲宽度是否大于最大时钟脉冲宽度。 在确定时钟脉冲宽度大于最大时钟脉冲宽度的情况下，时钟信号的时钟脉冲宽度受到限制。

公开(公告)号：US5801524A

公开(公告)日：1998-09-01

申请号：US863151

申请日：1997-05-27

申请人： David Boerstler

发明人： David Boerstler

IPC分类号： G05F3/24 ,  G05F3/26

CPC分类号： G05F3/247

摘要： A differential input, voltage controlled current source utilizing a low supply voltage and realizing a wide common mode input range. The voltage controlled current source provides a differential output current as a function the differential input voltage which is independent of the common mode input voltage level. The voltage controlled current source includes a first and a second differential amplifier receiving the differential input voltage and producing a differential current having a first and second leg. The first leg of the differential output current is tracked by a current mirror which floats as a function of the bias voltage and common mode input voltage. A second floating current mirror tracks the second differential output current leg. The first and second current mirrors are coupled to a replica bias circuit which is connected in parallel with the differential amplifiers. The replica bias and first and second current mirrors are connected across the supply voltage and not cascaded with other circuit functions, making the present invention compatible with low voltage technologies.

摘要翻译： 差分输入，压控电流源采用低电源电压并实现宽共模输入范围。 电压控制电流源提供差分输出电流作为独立于共模输入电压电平的差分输入电压的函数。 压控电流源包括接收差分输入电压的第一和第二差分放大器，并产生具有第一和第二支路的差动电流。 差分输出电流的第一段由电流镜跟踪，该电流镜根据偏置电压和共模输入电压而浮动。 第二个浮动电流镜跟踪第二差分输出电流支路。 第一和第二电流镜耦合到与差分放大器并联连接的复制偏置电路。 复制偏置和第一和第二电流镜跨电源电压连接，而不与其它电路功能级联，使得本发明与低电压技术兼容。

公开(公告)号：US20080111604A1

公开(公告)日：2008-05-15

申请号：US12014501

申请日：2008-01-15

申请人： David Boerstler ,  Eskinder Hailu ,  Byron Krauter ,  Kazuhiko Miki ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Byron Krauter ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： G06F1/10 ,  H03K5/1565

摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

摘要翻译： 提供了一种方法，装置和计算机程序来测量和/或校正占空比。 各种信号的占空比，特别是时钟信号是很重要的。 然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。 为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。