发明申请
US20070279964A1 SRAM split write control for a delay element 审中-公开
用于延迟元件的SRAM分离写入控制

SRAM split write control for a delay element
摘要:
A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.
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