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31 条记录 (耗时 0.017 秒)

    SRAM split write control for a delay element
    1.
    发明申请
    SRAM split write control for a delay element 审中-公开
    用于延迟元件的SRAM分离写入控制

    公开(公告)号：US20070279964A1

    公开(公告)日：2007-12-06

    申请号：US11440892

    申请日：2006-05-25

    申请人： Keith Golke ,  Harry Liu ,  David Nelson

    发明人： Keith Golke ,  Harry Liu ,  David Nelson

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/02 ,  G11C5/005 ,  G11C8/14 ,  G11C11/4125

    摘要： A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

    摘要翻译： 描述具有分离写入控制的静态随机存取存储器（SRAM）。 SRAM包括位，写和写字线。 SRAM内的每个存储单元包括耦合到专用写字线的延迟。 当单元未被写入时，其延迟在其相关联的写字线上接收延迟信号，这增加了单元的响应时间。 然而，当单元被写入时，其延迟在其相关的写字线上接收旁路信号，这降低了SRAM单元的响应时间。

    Radiation-hardened memory element with multiple delay elements
    2.
    发明申请
    Radiation-hardened memory element with multiple delay elements 有权
    具有多个延迟元件的辐射硬化存储元件

    公开(公告)号：US20070242537A1

    公开(公告)日：2007-10-18

    申请号：US11389767

    申请日：2006-03-27

    申请人： Keith Golke ,  Harry Liu ,  Michael Liu ,  David Nelson

    发明人： Keith Golke ,  Harry Liu ,  Michael Liu ,  David Nelson

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4125 ,  G11C5/005

    摘要： A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.

    摘要翻译： 辐射硬化的存储元件包括用于保持辐射硬度的至少两个延迟元件。 在一个示例中，存储器元件是SRAM单元。 两个延迟都串联在一起，使得如果任一个延迟失败，则在SRAM单元内仍将保持延迟。 延迟的关键区域可以定位成使得在每个延迟和电路节点之间不能产生共同的视线。

    SRAM Split Write Control for a Delay Element
    3.
    发明申请
    SRAM Split Write Control for a Delay Element 有权
    SRAM分离写延迟元件的写控制

    公开(公告)号：US20080106955A1

    公开(公告)日：2008-05-08

    申请号：US12013856

    申请日：2008-01-14

    申请人： Keith Golke ,  Harry Liu ,  David Nelson

    发明人： Keith Golke ,  Harry Liu ,  David Nelson

    IPC分类号： G11C7/00

    CPC分类号： G11C7/02 ,  G11C5/005 ,  G11C8/14 ,  G11C11/4125

    摘要： A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

    摘要翻译： 描述具有分离写入控制的静态随机存取存储器（SRAM）。 SRAM包括位，写和写字线。 SRAM内的每个存储单元包括耦合到专用写字线的延迟。 当单元未被写入时，其延迟在其相关联的写字线上接收延迟信号，这增加了单元的响应时间。 然而，当单元被写入时，其延迟在其相关的写字线上接收旁路信号，这降低了SRAM单元的响应时间。

    Dose rate simulation
    4.
    发明申请
    Dose rate simulation 有权
    剂量率模拟

    公开(公告)号：US20060145086A1

    公开(公告)日：2006-07-06

    申请号：US11029308

    申请日：2005-01-05

    申请人： Harry Liu ,  Keith Golke ,  Eric Vogt ,  Michael Liu

    发明人： Harry Liu ,  Keith Golke ,  Eric Vogt ,  Michael Liu

    IPC分类号： G01T1/24

    CPC分类号： G06F17/5036

    摘要： Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.

    摘要翻译： 在剂量率事件期间晶体管的行为可以使用电路仿真软件包进行建模。 子电路模型取代要仿真的电路设计中的晶体管。 子电路模型可以是基于原理图的表示形式或网表。 子电路模型在剂量率事件期间提供晶体管中的源极结和漏极结的模型。 子电路模型还包括被替换的晶体管的尺寸和剂量率事件的剂量率。 一旦晶体管被子电路模型替代，可以执行剂量率模拟来确定电路设计的剂量率硬度。

    SYSTEMS AND METHODS OF CELL SELECTION IN CROSS-POINT ARRAY MEMORY DEVICES
    5.
    发明申请
    SYSTEMS AND METHODS OF CELL SELECTION IN CROSS-POINT ARRAY MEMORY DEVICES 有权
    跨点阵列存储器件中的细胞选择的系统和方法

    公开(公告)号：US20110007538A1

    公开(公告)日：2011-01-13

    申请号：US12502111

    申请日：2009-07-13

    申请人： Chulmin Jung ,  Jinyoung Kim ,  Yong Lu ,  Harry Liu

    发明人： Chulmin Jung ,  Jinyoung Kim ,  Yong Lu ,  Harry Liu

    IPC分类号： G11C5/02 ,  G11C7/00

    CPC分类号： G11C13/0023 ,  G11C5/02 ,  G11C13/0038 ,  G11C2213/71

    摘要： The disclosure is related to three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).

    摘要翻译： 本公开涉及三维交叉点阵列存储器件并选择三维交叉点阵列存储器内的单元。 在特定实施例中，将三个不同的电压电平施加到交叉点阵列的位线以允许选择特定单元。 可以实现一系列选择装置以向特定位线提供高电压和低电压，同时还可以提供中间电压。 在特定实施例中，选择器件包括金属氧化物半导体场效应晶体管（MOSFET）。

    Systems and methods of cell selection in three-dimensional cross-point array memory devices
    9.
    发明授权
    Systems and methods of cell selection in three-dimensional cross-point array memory devices 有权
    三维交叉点阵列存储器件中细胞选择的系统和方法

    公开(公告)号：US08514637B2

    公开(公告)日：2013-08-20

    申请号：US12502111

    申请日：2009-07-13

    申请人： Chulmin Jung ,  Jinyoung Kim ,  Yong Lu ,  Harry Liu

    发明人： Chulmin Jung ,  Jinyoung Kim ,  Yong Lu ,  Harry Liu

    IPC分类号： G11C7/00

    CPC分类号： G11C13/0023 ,  G11C5/02 ,  G11C13/0038 ,  G11C2213/71

    摘要： Three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).

    摘要翻译： 三维交叉点阵列存储器件，并选择三维交叉点阵列存储器内的单元。 在特定实施例中，将三个不同的电压电平施加到交叉点阵列的位线以允许选择特定单元。 可以实现一系列选择装置以向特定位线提供高电压和低电压，同时还可以提供中间电压。 在特定实施例中，选择器件包括金属氧化物半导体场效应晶体管（MOSFET）。