发明申请
- 专利标题: Three Dimensional Six Surface Conformal Die Coating
- 专利标题(中): 三维六面共模模具涂层
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申请号: US11849162申请日: 2007-08-31
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公开(公告)号: US20070290377A1公开(公告)日: 2007-12-20
- 发明人: Al Vindasius , Marc Robinson
- 申请人: Al Vindasius , Marc Robinson
- 申请人地址: US CA Scotts Valley
- 专利权人: Vertical Circuits, Inc.
- 当前专利权人: Vertical Circuits, Inc.
- 当前专利权人地址: US CA Scotts Valley
- 主分类号: H01L23/29
- IPC分类号: H01L23/29 ; H01L21/56
摘要:
Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.
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