公开(公告)号：US07215018B2

公开(公告)日：2007-05-08

申请号：US11090969

申请日：2005-03-25

申请人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

发明人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

IPC分类号： H01L23/02

CPC分类号： H01L25/00 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011

摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

摘要翻译： 本发明提供一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。 延伸到模具或段的一个或多个侧面的金属重路由互连可以任选地添加到管芯或多管段中，以在管芯的表面上提供用于外部电连接点的边缘焊盘。 在金属重路由互连已经被添加到晶片上的管芯之后，晶片可选地变薄，并且通过切割或其他合适的分割方法将晶片从晶片上分离出来。 在从晶片上切割或切割管芯或多个管芯段之后，将绝缘施加到管芯或多个管芯段的所有表面上，在所需的电连接焊盘上方的绝缘体中形成开口，并且模具或多个管芯段是 放置在彼此的顶部以形成堆叠。 在堆叠中的垂直相邻的段通过将短的柔性接合线或粘合带附接到裸露的电连接焊盘而在模具的周边边缘处水平地插入并且施加导电聚合物或环氧树脂，细丝或线 到堆叠的一侧或多侧。

公开(公告)号：US20050258530A1

公开(公告)日：2005-11-24

申请号：US11097829

申请日：2005-03-31

申请人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

发明人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

IPC分类号： H01L23/02 ,  H01L23/495 ,  H01L25/065

CPC分类号： H01L23/49575 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2924/09701 ,  H01L2924/3011

摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

摘要翻译： 本发明提供一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。 延伸到模具或段的一个或多个侧面的金属重路由互连可以任选地添加到管芯或多管段中，以在管芯的表面上提供用于外部电连接点的边缘焊盘。 在金属重路由互连已经被添加到晶片上的管芯之后，晶片可选地变薄，并且通过切割或其他合适的分割方法将晶片从晶片上分离出来。 在从晶片上切割或切割管芯或多个管芯段之后，将绝缘施加到管芯或多个管芯段的所有表面上，在所需的电连接焊盘上方的绝缘体中形成开口，并且模具或多个管芯段是 放置在彼此的顶部以形成堆叠。 在堆叠中的垂直相邻的段通过将短的柔性接合线或粘合带附接到裸露的电连接焊盘而在模具的周边边缘处水平地插入并且施加导电聚合物或环氧树脂，细丝或线 到堆叠的一侧或多侧。

公开(公告)号：US20070252262A1

公开(公告)日：2007-11-01

申请号：US11744153

申请日：2007-05-03

申请人： Marc Robinson ,  Al Vindasius ,  Donald Almen ,  Larry Jacobsen

发明人： Marc Robinson ,  Al Vindasius ,  Donald Almen ,  Larry Jacobsen

IPC分类号： H01L25/00

CPC分类号： H01L23/49575 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2924/09701 ,  H01L2924/3011

摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

摘要翻译： 本发明提供一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。 延伸到模具或段的一个或多个侧面的金属重路由互连可以任选地添加到管芯或多管段中，以在管芯的表面上提供用于外部电连接点的边缘焊盘。 在金属重路由互连已经被添加到晶片上的管芯之后，晶片可选地变薄，并且通过切割或其他合适的分割方法将晶片从晶片上分离出来。 在从晶片上切割或切割管芯或多个管芯段之后，将绝缘施加到管芯或多个管芯段的所有表面上，在所需的电连接焊盘上方的绝缘体中形成开口，并且模具或多个管芯段是 放置在彼此的顶部以形成堆叠。 在堆叠中的垂直相邻的段通过将短的柔性接合线或粘合带附接到裸露的电连接焊盘而在模具的周边边缘处水平地插入并且施加导电聚合物或环氧树脂，细丝或线 到堆叠的一侧或多侧。

公开(公告)号：US20050230802A1

公开(公告)日：2005-10-20

申请号：US11090969

申请日：2005-03-25

申请人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

发明人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

IPC分类号： H01L21/56 ,  H01L23/02 ,  H01L23/31 ,  H01L23/525 ,  H01L25/065

CPC分类号： H01L25/00 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011

摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

摘要翻译： 本发明提供一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。 延伸到模具或段的一个或多个侧面的金属重路由互连可以任选地添加到管芯或多管段中，以在管芯的表面上提供用于外部电连接点的边缘焊盘。 在金属重路由互连已经被添加到晶片上的管芯之后，晶片可选地变薄，并且通过切割或其他合适的分割方法将晶片从晶片上分离出来。 在从晶片上切割或切割管芯或多个管芯段之后，将绝缘施加到管芯或多个管芯段的所有表面上，在所需的电连接焊盘上方的绝缘体中形成开口，并且模具或多个管芯段是 放置在彼此的顶部以形成堆叠。 在堆叠中的垂直相邻的段通过将短的柔性接合线或粘合带附接到裸露的电连接焊盘而在模具的外围边缘处水平地从模具突出并且施加导电聚合物或环氧树脂，细丝或线 到堆叠的一侧或多侧。

公开(公告)号：US07705432B2

公开(公告)日：2010-04-27

申请号：US11016558

申请日：2004-12-17

申请人： Al Vindasius ,  Marc Robinson

发明人： Al Vindasius ,  Marc Robinson

IPC分类号： H01L23/58

CPC分类号： H01L23/3185 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

摘要翻译： 半导体管芯通常被制造为通过光刻装置在半导体晶片或硅片上成像的大量集成电路管芯。 在制造之后，硅晶片通常通过机械方式变薄，并且通常使用金刚石锯将晶片切割成单个模具。 所得到的单个集成电路具有六个暴露表面。 芯片的顶表面包括电路图像和在晶片制造期间已被添加到顶层的任何钝化层。 本发明描述了一种用于保护和绝缘模具的所有六个表面以减少断裂的方法，为这些层提供电绝缘，并提供可用于将一个半导体管芯与另一个半导体管芯结合的物理表面，用于将模具堆叠 互连的模块或组件。

公开(公告)号：US20070290377A1

公开(公告)日：2007-12-20

申请号：US11849162

申请日：2007-08-31

申请人： Al Vindasius ,  Marc Robinson

发明人： Al Vindasius ,  Marc Robinson

IPC分类号： H01L23/29 ,  H01L21/56

CPC分类号： H01L23/3185 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

摘要翻译： 半导体管芯通常被制造为通过光刻装置在半导体晶片或硅片上成像的大量集成电路管芯。 在制造之后，通常通过机械方式使硅晶片变薄，并且通常使用金刚石锯将晶片切割成单个模具。 所得到的单个集成电路具有六个暴露表面。 芯片的顶表面包括电路图像和在晶片制造期间已被添加到顶层的任何钝化层。 本发明描述了一种用于保护和绝缘模具的所有六个表面以减少断裂的方法，为这些层提供电绝缘，并提供用于将一个半导体管芯与另一个半导体管芯结合的物理表面，用于将模具堆叠 互连的模块或组件。

公开(公告)号：US20070284716A1

公开(公告)日：2007-12-13

申请号：US11744142

申请日：2007-05-03

申请人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

发明人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

IPC分类号： H01L23/522

CPC分类号： H01L25/00 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011

摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack

摘要翻译： 本发明提供一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。 延伸到模具或段的一个或多个侧面的金属重路由互连可以任选地添加到管芯或多管段中，以在管芯的表面上提供用于外部电连接点的边缘焊盘。 在金属重路由互连已经被添加到晶片上的管芯之后，晶片可选地变薄，并且通过切割或其他合适的分割方法将晶片从晶片上分离出来。 在从晶片上切割或切割管芯或多个管芯段之后，将绝缘施加到管芯或多个管芯段的所有表面上，在所需的电连接焊盘上方的绝缘体中形成开口，并且模具或多个管芯段是 放置在彼此的顶部以形成堆叠。 在堆叠中的垂直相邻的段通过将短的柔性接合线或粘合带附接到裸露的电连接焊盘而在模具的外围边缘处水平地从模具突出并且施加导电聚合物或环氧树脂，细丝或线 到堆叠的一侧或多侧

公开(公告)号：US07245021B2

公开(公告)日：2007-07-17

申请号：US11097829

申请日：2005-03-31

申请人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

发明人： Al Vindasius ,  Marc Robinson ,  Larry Jacobsen ,  Donald Almen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49575 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2924/09701 ,  H01L2924/3011

摘要： The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

摘要翻译： 本发明提供一种用于垂直互连半导体管芯，集成电路管芯或多个管芯段的装置。 延伸到模具或段的一个或多个侧面的金属重路由互连可以任选地添加到管芯或多管段中，以在管芯的表面上提供用于外部电连接点的边缘焊盘。 在金属重路由互连已经被添加到晶片上的管芯之后，晶片可选地变薄，并且通过切割或其他合适的分割方法将晶片从晶片上分离出来。 在从晶片上切割或切割管芯或多个管芯段之后，将绝缘施加到管芯或多个管芯段的所有表面上，在所需的电连接焊盘上方的绝缘体中形成开口，并且模具或多个管芯段是 放置在彼此的顶部以形成堆叠。 在堆叠中的垂直相邻的段通过将短的柔性接合线或粘合带附接到裸露的电连接焊盘而在模具的外围边缘处水平地从模具突出并且施加导电聚合物或环氧树脂，细丝或线 到堆叠的一侧或多侧。

公开(公告)号：US20050224952A1

公开(公告)日：2005-10-13

申请号：US11016558

申请日：2004-12-17

申请人： Al Vindasius ,  Marc Robinson

发明人： Al Vindasius ,  Marc Robinson

IPC分类号： H01L23/053 ,  H01L23/31

CPC分类号： H01L23/3185 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

摘要翻译： 半导体管芯通常被制造为通过光刻装置在半导体晶片或硅片上成像的大量集成电路管芯。 在制造之后，硅晶片通常通过机械方式变薄，并且通常使用金刚石锯将晶片切割成单个模具。 所得到的单个集成电路具有六个暴露表面。 芯片的顶表面包括电路图像和在晶片制造期间已被添加到顶层的任何钝化层。 本发明描述了一种用于保护和绝缘模具的所有六个表面以减少断裂的方法，为这些层提供电绝缘，并提供用于将一个半导体管芯与另一个半导体管芯结合的物理表面，用于将模具堆叠 互连的模块或组件。

公开(公告)号：US20130067693A1

公开(公告)日：2013-03-21

申请号：US13565712

申请日：2012-08-02

申请人： Marc Robinson

发明人： Marc Robinson

IPC分类号： A44B11/25

CPC分类号： A41B1/08 ,  A41B1/18 ,  Y10T24/3606 ,  Y10T24/3651

摘要： There is disclosed a garment closure comprising a front component, a rear component and an intermediate connector component. The connector component fastens the front component and the rear component together so that the front component and rear component are in spaced relationship relative to each other. The rear component is configured for insertion through a fastener aperture.

摘要翻译： 公开了一种衣服封口，其包括前部部件，后部部件和中间连接器部件。 连接器部件将前部部件和后部部件固定在一起，使得前部部件和后部部件相对于彼此成间隔开的关系。 后部构件构造成用于插入穿过紧固件孔。