- 专利标题: Semiconductor integrated circuit with PLL circuit
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申请号: US11896665申请日: 2007-09-05
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公开(公告)号: US20080012650A1公开(公告)日: 2008-01-17
- 发明人: Jiro Shinbo , Satoshi Arayashiki , Hirotaka Oosawa , Toshiya Uozumi , Satoru Yamamoto
- 申请人: Jiro Shinbo , Satoshi Arayashiki , Hirotaka Oosawa , Toshiya Uozumi , Satoru Yamamoto
- 优先权: JP2004-205452 20040713
- 主分类号: H03L7/00
- IPC分类号: H03L7/00
摘要:
In a PLL circuit including an oscillator, a phase comparator, a charge pump circuit, and a loop filter, without providing a plurality of capacitative elements, that is, without increasing the occupied area so much, the characteristics of the PLL circuit can be adjusted according to manufacture variations in a resistive element and a capacitative element, and a loop filter can be formed on a chip. A resistive element and a capacitative element of a loop filter are formed on a semiconductor chip. As the resistive element, a plurality of elements having different resistance values are provided and switched by a switch, thereby enabling the resistance value to be adjusted. Current in a charge pump circuit is also made adjustable, and the current of the charge pump circuit is adjusted according to switching among the resistance values of the resistive elements.
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