Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.