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    Configurable IC's With Configurable Logic Resources That Have Asymmetric Inputs And/Or Outputs
    1.
    发明申请
    Configurable IC's With Configurable Logic Resources That Have Asymmetric Inputs And/Or Outputs 有权

    公开(公告)号：US20080018359A1

    公开(公告)日：2008-01-24

    申请号：US11775218

    申请日：2007-07-09

    申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Huang ,  Jason Redgrave

    发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Huang ,  Jason Redgrave

    IPC分类号： H03K19/177

    CPC分类号： H01L25/065 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11898 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/17796 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.

    Configurable IC with configurable routing resources that have asymmetric Input and/or outputs
    2.
    发明申请
    Configurable IC with configurable routing resources that have asymmetric Input and/or outputs 有权
    具有可配置路由资源的可配置IC，具有非对称的输入和/或输出

    公开(公告)号：US20070244961A1

    公开(公告)日：2007-10-18

    申请号：US11082225

    申请日：2005-03-15

    申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Huang ,  Jason Redgrave

    发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Huang ,  Jason Redgrave

    IPC分类号： G06F7/50

    CPC分类号： G06F7/506 ,  G06F2207/3868 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. Each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable routing interconnect circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any routing circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular routing circuit in any interior tile and any circuit that provides an input of the particular routing circuit.

    摘要翻译： 一些实施例提供了包括若干可配置瓦片的可配置IC。 可配置瓦片包括可配置瓦片布置内部的若干内部瓦片。 该布置具有限定布置的外部边界的几个边。 每个可配置内部瓦片包括一组可配置逻辑电路和一组可配置的路由互连电路，用于在可配置逻辑电路之间路由信号。 每个内部瓦片中的一组可配置路由互连电路具有由可配置IC中的一组不对称位置提供的一组输入。 任何内部瓦片中的任何路线电路与瓦片布置的任何边界限定侧之间的任何距离大于任何内部瓦片中的任何特定路由电路与提供特定路由电路的输入的任何电路之间的任何距离。

    System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture
    3.
    发明授权
    System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture 有权
    用于提供比物理存储器架构更窄和更深的虚拟存储器架构的系统和方法

    公开(公告)号：US07962705B2

    公开(公告)日：2011-06-14

    申请号：US12729227

    申请日：2010-03-22

    申请人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

    发明人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

    IPC分类号： G06F9/315

    CPC分类号： H03K19/17736 ,  H03K19/1776

    摘要： Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

    摘要翻译： 一些实施例提供了一种呈现比物理存储器更窄和更深的虚拟存储器的方法。 该方法接收包括一组实际存储器地址位和一组虚拟存储器位置位的存储器地址位置。 该方法使用实际存储器地址位从物理存储器中检索原始存储器字。 该方法通过使用桶形移位器将原始存储器字移动由虚拟存储器位置位确定的量，创建移位的存储器字。 该方法读取移位的存储器字的一部分。

    Retrieving data from a configurable IC
    4.
    发明授权
    Retrieving data from a configurable IC 有权
    从可配置IC检索数据

    公开(公告)号：US07595655B2

    公开(公告)日：2009-09-29

    申请号：US11769686

    申请日：2007-06-27

    申请人： Brad Hutchings ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave

    发明人： Brad Hutchings ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave

    IPC分类号： H03K19/00 ,  G06F17/50

    CPC分类号： H03K19/17764 ,  H03K19/17736

    摘要： Some embodiments provide a configurable integrated circuit (IC). The IC has configurable logic circuits for performing logical operations, configurable routing circuits for routing signals between the configurable logic circuits, and a network for monitoring data. In some embodiments a method uses at least a subset of the configurable logic circuits and a first subset of the configurable routing circuits to implement a user design circuit on the configurable IC. The method uses a second subset of the configurable routing circuits to pass signals to the network.

    摘要翻译： 一些实施例提供可配置集成电路（IC）。 IC具有用于执行逻辑操作的可配置逻辑电路，用于在可配置逻辑电路之间路由信号的可配置路由电路以及用于监视数据的网络。 在一些实施例中，一种方法使用可配置逻辑电路的至少一个子集和可配置路由电路的第一子集来实现可配置IC上的用户设计电路。 该方法使用可配置路由电路的第二子集将信号传递到网络。

    Sub-cycle configurable hybrid logic/interconnect circuit
    5.
    发明授权
    Sub-cycle configurable hybrid logic/interconnect circuit 有权
    子周期可配置混合逻辑/互连电路

    公开(公告)号：US07307449B1

    公开(公告)日：2007-12-11

    申请号：US11269168

    申请日：2005-11-07

    申请人： Jason Redgrave ,  Brad Hutchings ,  Herman Schmit ,  Steven Teig

    发明人： Jason Redgrave ,  Brad Hutchings ,  Herman Schmit ,  Steven Teig

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17796

    摘要： Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.

    摘要翻译： 本发明的一些实施例提供了可配置的集成电路（“IC”）。 该IC包括用于接收配置数据并且可配置地基于配置数据执行一组操作的多个可配置电路。 它还包括几个混合电路。 每个特定的混合电路可以互换地作为可配置IC中的逻辑电路或互连电路执行。

    SYSTEM AND METHOD FOR PROVIDING A VIRTUAL MEMORY ARCHITECTURE NARROWER AND DEEPER THAN A PHYSICAL MEMORY ARCHITECTURE
    6.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING A VIRTUAL MEMORY ARCHITECTURE NARROWER AND DEEPER THAN A PHYSICAL MEMORY ARCHITECTURE 有权
    提供虚拟存储器架构的系统和方法和深度超过物理存储器架构的系统和方法

    公开(公告)号：US20100241800A1

    公开(公告)日：2010-09-23

    申请号：US12729227

    申请日：2010-03-22

    申请人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

    发明人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

    IPC分类号： G06F12/00 ,  G06F9/315

    CPC分类号： H03K19/17736 ,  H03K19/1776

    摘要： Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

    摘要翻译： 一些实施例提供了一种呈现比物理存储器更窄和更深的虚拟存储器的方法。 该方法接收包括一组实际存储器地址位和一组虚拟存储器位置位的存储器地址位置。 该方法使用实际存储器地址位从物理存储器中检索原始存储器字。 该方法通过使用桶形移位器将原始存储器字移动由虚拟存储器位置位确定的量，创建移位的存储器字。 该方法读取移位的存储器字的一部分。

    Accessing multiple user states concurrently in a configurable IC
    7.
    发明授权
    Accessing multiple user states concurrently in a configurable IC 有权
    在可配置的IC中同时访问多个用户状态

    公开(公告)号：US07788478B2

    公开(公告)日：2010-08-31

    申请号：US11375562

    申请日：2006-03-13

    申请人： Jason Redgrave ,  Brad Hutchings ,  Steven Teig ,  Herman Schmit ,  Teju Khubchandani

    发明人： Jason Redgrave ,  Brad Hutchings ,  Steven Teig ,  Herman Schmit ,  Teju Khubchandani

    IPC分类号： H03K19/00

    CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

    摘要： Some embodiments of the invention provide a configuration/debug network for configuring and debugging a configurable integrated circuit (IC). The configurable IC in some embodiments includes configurable resources (e.g., configurable logic resources, routing resources, memory resources, etc.) that can be grouped in conceptual configurable tiles that are arranged in several rows and columns. Some embodiments allow tiles to be individually addressed, globally addressed (i.e., all addressed together), or addressed based on their tile types. The configurable IC includes numerous user-design state elements (“UDS elements”) in some embodiments. In some embodiments, the configuration/debug network has a streaming mode that can direct various circuits in one or more configurable tiles to stream out their data during the operation of the configurable IC. Accordingly, in the embodiments where the configuration/debug network connects to some or all of the UDS elements, the configurable/debug network can be used in a streaming mode to stream out data from the UDS elements of the tiles, in order to identify any errors in the operation of the IC. In other words, the streaming of the data from the UDS elements can be used to debug the operation of the configurable IC. In some embodiments, the configuration/debug network has a broadcasting mode that can direct various resources (e.g., memories, storage elements, etc.) in one or more configurable tiles to store the same data. For instance, the broadcasting mode can be used to initialize the memory blocks in the configurable memory tiles.

    摘要翻译： 本发明的一些实施例提供了用于配置和调试可配置集成电路（IC）的配置/调试网络。 在一些实施例中，可配置IC包括可被分组在以多行和列排列的概念可配置瓦片中的可配置资源（例如，可配置逻辑资源，路由资源，存储器资源等）。 一些实施例允许瓦片被单独寻址，全局寻址（即，全部寻址在一起）或基于它们的瓦片类型寻址。 在一些实施例中，可配置IC包括许多用户设计状态元件（“UDS元件”）。 在一些实施例中，配置/调试网络具有流模式，其可以在一个或多个可配置瓦片中引导各种电路以在可配置IC的操作期间流出其数据。 因此，在配置/调试网络连接到一些或所有UDS元件的实施例中，可配置/调试网络可以以流模式用于从瓦片的UDS元件流出数据，以便识别任何 IC的运行错误。 换句话说，来自UDS元件的数据流可用于调试可配置IC的操作。 在一些实施例中，配置/调试网络具有可以将一些或多个可配置瓦片中的各种资源（例如，存储器，存储元件等）引导以存储相同数据的广播模式。 例如，可以使用广播模式来初始化可配置存储器块中的存储器块。

    Runtime loading of configuration data in a configurable IC
    8.
    发明授权
    Runtime loading of configuration data in a configurable IC 失效
    可配置IC中的配置数据的运行时加载

    公开(公告)号：US07696780B2

    公开(公告)日：2010-04-13

    申请号：US12106257

    申请日：2008-04-18

    申请人： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

    发明人： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K19/17776 ,  G06F7/32 ,  G06F7/764 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17764

    摘要： Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network.

    摘要翻译： 本发明的一些实施例提供了一种可配置集成电路（IC），其具有用于可配置地执行不同操作的多个可配置电路。 在IC的操作期间，每个特定可配置电路执行由针对特定可配置电路的特定配置数据集指定的特定操作。 当IC操作并且第一组可配置电路执行第一组操作时，从IC的外部加载配置数据，用于配置第二组可配置电路。 在一些实施例中，可配置IC包括用于从IC外部快速加载IC中的配置数据的配置网络。 在这些实施例中的一些实施例中，配置网络是流水线网络。 此外，一些实施例的IC包括用于从IC外部检索配置数据的配置控制器，配置数据组，以及通过配置网络将配置数据集路由到第二组可配置电路。

    System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture
    9.
    发明授权
    System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture 失效
    用于提供比物理存储器架构更窄和更深的虚拟存储器架构的系统和方法

    公开(公告)号：US07694083B1

    公开(公告)日：2010-04-06

    申请号：US11371352

    申请日：2006-03-08

    申请人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

    发明人： Herman Schmit ,  Andrew Caldwell ,  Brad Hutchings ,  Jason Redgrave ,  Steven Teig

    IPC分类号： G06F9/315

    CPC分类号： H03K19/17736 ,  H03K19/1776

    摘要： Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

    摘要翻译： 一些实施例提供了一种呈现比物理存储器更窄和更深的虚拟存储器的方法。 该方法接收包括一组实际存储器地址位和一组虚拟存储器位置位的存储器地址位置。 该方法使用实际存储器地址位从物理存储器中检索原始存储器字。 该方法通过使用桶形移位器将原始存储器字移动由虚拟存储器位置位确定的量，创建移位的存储器字。 该方法读取移位的存储器字的一部分。