发明申请
US20080029756A1 Semiconductor buffer architecture for III-V devices on silicon substrates
有权
硅衬底上III-V器件的半导体缓冲架构
- 专利标题： Semiconductor buffer architecture for III-V devices on silicon substrates
- 专利标题（中）： 硅衬底上III-V器件的半导体缓冲架构
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申请号： US11498685申请日： 2006-08-02
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公开(公告)号： US20080029756A1公开(公告)日： 2008-02-07
- 发明人: Mantu K. Hudait , Mohamad A. Shaheen , Dmitri Loubychev , Amy W.K. Liu , Joel M. Fastenau
- 申请人： Mantu K. Hudait , Mohamad A. Shaheen , Dmitri Loubychev , Amy W.K. Liu , Joel M. Fastenau
- 主分类号： H01L29/12
- IPC分类号： H01L29/12 ; H01L21/20
摘要：
A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.
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