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    Semiconductor buffer architecture for III-V devices on silicon substrates
    2.
    发明申请
    Semiconductor buffer architecture for III-V devices on silicon substrates 有权
    硅衬底上III-V器件的半导体缓冲架构

    公开(公告)号：US20080029756A1

    公开(公告)日：2008-02-07

    申请号：US11498685

    申请日：2006-08-02

    申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Dmitri Loubychev ,  Amy W.K. Liu ,  Joel M. Fastenau

    发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Dmitri Loubychev ,  Amy W.K. Liu ,  Joel M. Fastenau

    IPC分类号： H01L29/12 ,  H01L21/20

    CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/1029 ,  H01L29/812

    摘要： A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.

    摘要翻译： 描述了用于在硅衬底上形成III-V器件层的复合缓冲结构及其制造方法。 本发明的实施方案能够在硅衬底上形成缺陷密度低于1×10 8 cm -2的III-V InSb器件层。 在本发明的一个实施例中，双缓冲层位于III-V器件层和硅衬底之间以滑动位错并提供电隔离。 在本发明的一个实施例中，基于晶格常数，带隙和熔点选择每个缓冲层的材料，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。 在具体实施方式中，GaSb / AlSb缓冲器用于在硅衬底上形成基于InSb的量子阱晶体管。

    Semiconductor buffer architecture for III-V devices on silicon substrates
    6.
    发明授权
    Semiconductor buffer architecture for III-V devices on silicon substrates 有权
    硅衬底上III-V器件的半导体缓冲架构

    公开(公告)号：US08034675B2

    公开(公告)日：2011-10-11

    申请号：US12915557

    申请日：2010-10-29

    申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Dmitri Loubychev ,  Amy W. K. Liu ,  Joel M. Fastenau

    发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Dmitri Loubychev ,  Amy W. K. Liu ,  Joel M. Fastenau

    IPC分类号： H01L21/338

    CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/1029 ,  H01L29/812

    摘要： A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.

    摘要翻译： 描述了用于在硅衬底上形成III-V器件层的复合缓冲结构及其制造方法。 本发明的实施方案能够在硅衬底上形成缺陷密度低于1×10 8 cm -2的III-V InSb器件层。 在本发明的一个实施例中，双缓冲层位于III-V器件层和硅衬底之间以滑动位错并提供电隔离。 在本发明的一个实施例中，基于晶格常数，带隙和熔点选择每个缓冲层的材料，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。 在具体实施方式中，GaSb / AlSb缓冲器用于在硅衬底上形成基于InSb的量子阱晶体管。

    SEMICONDUCTOR BUFFER ARCHITECTURE FOR III-V DEVICES ON SILICON SUBSTRATES
    9.
    发明申请
    SEMICONDUCTOR BUFFER ARCHITECTURE FOR III-V DEVICES ON SILICON SUBSTRATES 有权
    硅衬底上III-V器件的半导体缓冲器架构

    公开(公告)号：US20110045659A1

    公开(公告)日：2011-02-24

    申请号：US12915557

    申请日：2010-10-29

    申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Dmitri Loubychev ,  Amy W. K. Liu ,  Joel M. Fastenau

    发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Dmitri Loubychev ,  Amy W. K. Liu ,  Joel M. Fastenau

    IPC分类号： H01L21/20

    CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/1029 ,  H01L29/812

    摘要： A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.

    摘要翻译： 描述了用于在硅衬底上形成III-V器件层的复合缓冲结构及其制造方法。 本发明的实施方案能够在硅衬底上形成缺陷密度低于1×10 8 cm -2的III-V InSb器件层。 在本发明的一个实施例中，双缓冲层位于III-V器件层和硅衬底之间以滑动位错并提供电隔离。 在本发明的一个实施例中，基于晶格常数，带隙和熔点选择每个缓冲层的材料，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。 在具体实施方式中，GaSb / AlSb缓冲器用于在硅衬底上形成基于InSb的量子阱晶体管。