发明申请
- 专利标题： Clock data recovery circuitry associated with programmable logic device circuitry
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申请号： US11796136申请日： 2007-04-25
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公开(公告)号： US20080031385A1公开(公告)日： 2008-02-07
- 发明人: Edward Aung , Henry Lui , Paul Butler , John Turner , Rakesh Patel , Chong Lee
- 申请人： Edward Aung , Henry Lui , Paul Butler , John Turner , Rakesh Patel , Chong Lee
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 主分类号： H03K9/00
- IPC分类号： H03K9/00
摘要：
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.
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