Invention Application
- Patent Title: Package with solder-filled via holes in molding layers
- Patent Title (中): 封装在成型层中的焊料填充通孔
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Application No.: US11880753Application Date: 2007-07-23
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Publication No.: US20080036050A1Publication Date: 2008-02-14
- Inventor: Paul T. Lin , Chi-Shih Chang
- Applicant: Paul T. Lin , Chi-Shih Chang
- Main IPC: H01L23/48
- IPC: H01L23/48 ; B29C45/34 ; H01L23/552 ; H01L21/50

Abstract:
The present invention discloses an electronic package to contain and protect an integrated circuit (IC) chip. The electronic package further includes a leadframe, a flexible circuit or PCB type of substrate. The leadframe, flexible circuit or PCB type substrate further includes solder contacts, which are aligned with via holes in the molding layers on the top and bottom sides of the package. These via holes are for placing solder paste or solder balls from above and below for electrical access to the IC chip. These solder balls provide access for electrical testing after the package is mounted on a motherboard. They also provide the connection points for stacking multiple packages vertically.
Public/Granted literature
- US07667338B2 Package with solder-filled via holes in molding layers Public/Granted day:2010-02-23
Information query
IPC分类: