The present invention relates to an integrated circuit comprising a plurality of processing modules (M, S) and an interconnect means (N) for coupling said plurality of processing modules (M, S) and for enabling a packet based communication based on transactions between said plurality of processing modules (M, S). Each packet comprises a number of subsequent words. A first of said plurality of processing modules (M) issues a transaction by sending a plurality of messages (msg1, msg2) over said interconnect means (N) to a second of said plurality of processing modules (S). At least one packet inspecting unit (PIU) is provided for packetizing said plurality of messages (msg1, msg2) into a plurality of packets and for inspecting said packets in order to determine unused space in said packets and to fill up said unused space with data from at least one subsequent message (msg1, msg2).