发明申请
- 专利标题： Top Layers of Metal for Integrated Circuits
- 专利标题（中）： 集成电路金属顶层
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申请号： US11877657申请日： 2007-10-23
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公开(公告)号： US20080045007A1公开(公告)日： 2008-02-21
- 发明人: Mou-Shiung Lin , Chiu-Ming Chou , Chien-Kang Chou
- 申请人： Mou-Shiung Lin , Chiu-Ming Chou , Chien-Kang Chou
- 申请人地址： TW Hsinchu 300
- 专利权人： MEGICA CORPORATION
- 当前专利权人： MEGICA CORPORATION
- 当前专利权人地址： TW Hsinchu 300
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763
摘要：
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.
公开/授权文献
- US07482268B2 Top layers of metal for integrated circuits 公开/授权日：2009-01-27
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