公开(公告)号：US08884433B2

公开(公告)日：2014-11-11

申请号：US12545880

申请日：2009-08-24

申请人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

发明人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC分类号： H01L29/40 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L24/12 ,  H01L21/76801 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/53295 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/45183 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/05599

摘要： A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.

摘要翻译： 电路结构包括半导体衬底，半导体衬底上的第一和第二金属柱，半导体衬底上的绝缘层，并覆盖第一和第二金属柱，第一和第二金属柱上的第一和第二凸起或绝缘层 。 第一和第二金属柱的高度为20至300微米，其最大水平尺寸与其高度之比小于4.第一凸起的中心与第二凸起的中心之间的距离 在10和250微米之间。

公开(公告)号：US08362588B2

公开(公告)日：2013-01-29

申请号：US13159147

申请日：2011-06-13

申请人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

发明人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

IPC分类号： H01L29/00 ,  H01L23/52 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

公开(公告)号：US08148822B2

公开(公告)日：2012-04-03

申请号：US11383762

申请日：2006-05-17

申请人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

发明人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L23/525 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13183 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.

摘要翻译： 在具有至少在其顶表面上的接触层的集成电路（IC）衬底上制造焊盘结构。 钝化层覆盖IC基板的顶表面和接触层。 钝化层具有露出接触层的一部分的开口。 导电性粘合/阻挡层直接接合到接触层。 导电粘合/阻挡层延伸到钝化层的顶表面。 接合金属层层叠在导电性粘接/阻挡层上。

公开(公告)号：US08120181B2

公开(公告)日：2012-02-21

申请号：US12182148

申请日：2008-07-30

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou

IPC分类号： H01L27/10

CPC分类号： H01L23/5329 ,  H01L23/3171 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/01019 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/014 ,  H01L2924/00012

摘要： A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

摘要翻译： 描述了用于形成后钝化金属结构的系统和方法。 金属互连和高质量的电气部件，例如电感器，变压器，电容器或电阻器形成在钝化层上，或者在钝化层上的厚层聚合物上。

公开(公告)号：US20110266680A1

公开(公告)日：2011-11-03

申请号：US13180479

申请日：2011-07-11

申请人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Hsin-Jung Lo

发明人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Hsin-Jung Lo

IPC分类号： H01L23/532 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/288 ,  H01L21/76838 ,  H01L23/5227 ,  H01L23/53223 ,  H01L23/53276 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/48 ,  H01L2221/1094 ,  H01L2224/02166 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/451 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099

摘要： The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.

摘要翻译： 本发明提出了一种电路部件结构，其包括半导体衬底，形成在半导体衬底上并具有至少一个金属焊盘的细线金属化结构，形成在细线金属化结构上的钝化层，金属焊盘暴露 通过钝化层的开口，形成在细线金属化结构上的至少一个碳纳米管层和钝化层并与金属焊盘连接。 本发明提供一种碳纳米管回路部件结构及其制造方法，其中，半导体元件的电路由导电性碳纳米管构成，能够使半导体元件的电路变得更细且更致密 通过优异的导电性，柔性和碳纳米管的强度。

公开(公告)号：US07977803B2

公开(公告)日：2011-07-12

申请号：US12941069

申请日：2010-11-07

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/43

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

摘要翻译： 一种芯片结构，包括硅衬底，MOS器件，电介质层，金属化结构，钝化层，多个金属层和聚合物层。 金属化结构包括在第一电路层上的第一电路层和第二电路层，并且包括镶嵌电镀铜。 钝化层在金属化结构和电介质层之上，钝化层包括暴露金属化结构的接触点的第一开口。 聚合物层设置在钝化层和第一金属层之上，聚合物层中的第二开口在第一金属层的第二接触点之上，聚合物层覆盖第一金属层的顶表面和侧壁。 第二接触点通过第一开口连接到第一接触点，第二开口不垂直于第一开口。

公开(公告)号：US07969006B2

公开(公告)日：2011-06-28

申请号：US11864917

申请日：2007-09-29

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Chien-Kang Chou

IPC分类号： H01L23/48

CPC分类号： H01L23/552 ,  H01L21/76816 ,  H01L21/76873 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L27/0251 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48764 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/01039 ,  H01L2924/00 ,  H01L2224/05552

摘要： An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

公开(公告)号：US07964973B2

公开(公告)日：2011-06-21

申请号：US12202342

申请日：2008-09-01

申请人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Hsin-Jung Lo

发明人： Mou-Shiung Lin ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Hsin-Jung Lo

IPC分类号： H01L21/40

CPC分类号： H01L23/53238 ,  H01L23/3192 ,  H01L23/53252 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/056 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/48463 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/01039 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.

摘要翻译： 一种用于制造金属化结构的方法包括沉积第一金属层; 在所述第一金属层上沉积第一图案界定层，所述第一图案限定层中的第一开口暴露所述第一金属层; 在由所述第一开口暴露的所述第一金属层上沉积第二金属层; 在所述第二金属层上沉积第二图案限定层，所述第二图案限定层中的第二开口露出所述第二金属层; 在由所述第二开口暴露的所述第二金属层上沉积第三金属层; 去除所述第二图案限定层; 去除所述第一图案限定层; 以及不在所述第二金属层下方去除所述第一金属层。

公开(公告)号：US20090309224A1

公开(公告)日：2009-12-17

申请号：US12545880

申请日：2009-08-24

申请人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

发明人： Mou-Shiung Lin ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC分类号： H01L23/522

CPC分类号： H01L24/12 ,  H01L21/76801 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/53295 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45176 ,  H01L2224/45183 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/05599

摘要： A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.

摘要翻译： 电路结构包括半导体衬底，半导体衬底上的第一和第二金属柱，半导体衬底上的绝缘层，并覆盖第一和第二金属柱，第一和第二金属柱上的第一和第二凸起或绝缘层 。 第一和第二金属柱的高度为20至300微米，其最大水平尺寸与其高度之比小于4.第一凸起的中心与第二凸起的中心之间的距离 在10和250微米之间。

公开(公告)号：US20090218687A1

公开(公告)日：2009-09-03

申请号：US12464896

申请日：2009-05-13

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

IPC分类号： H01L23/498

CPC分类号： H01L24/06 ,  H01L21/76801 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

摘要翻译： 本发明提供一种半导体芯片，其包括半导体衬底，该半导体衬底包括MOS器件，在所述半导体衬底上的互连结构以及在所述MOS器件上方的金属凸块，其中所述金属凸块具有大于50重量％的金， 介于8和50微米之间。