The present invention relates to an apparatus and a method thereof for generating a clock signal. The apparatus includes a clock generating module and at least one delay stage. The clock generating module receives a reference signal through a first signal path, receives a feedback signal through a second signal path, and provides a clock signal to a third signal path according to the reference signal, wherein the feedback signal corresponds to the clock signal. The at least one delay stage is located on at least one of the first, second, and third signal paths for providing a corresponding delay on the signal path at which the at least one delay stage is positioned.