发明申请
US20080057705A1 TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS
有权
在层间电介质中形成VIAS期间减少等离子体诱导的蚀刻损伤的技术
- 专利标题: TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS
- 专利标题(中): 在层间电介质中形成VIAS期间减少等离子体诱导的蚀刻损伤的技术
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申请号: US11696226申请日: 2007-04-04
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公开(公告)号: US20080057705A1公开(公告)日: 2008-03-06
- 发明人: Frank Feustel , Kai Frohberg , Thomas Werner
- 申请人: Frank Feustel , Kai Frohberg , Thomas Werner
- 优先权: DE102006041004.1 20060831
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.
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