发明申请
US20080057705A1 TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS 有权
在层间电介质中形成VIAS期间减少等离子体诱导的蚀刻损伤的技术

  • 专利标题: TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS
  • 专利标题(中): 在层间电介质中形成VIAS期间减少等离子体诱导的蚀刻损伤的技术
  • 申请号: US11696226
    申请日: 2007-04-04
  • 公开(公告)号: US20080057705A1
    公开(公告)日: 2008-03-06
  • 发明人: Frank FeustelKai FrohbergThomas Werner
  • 申请人: Frank FeustelKai FrohbergThomas Werner
  • 优先权: DE102006041004.1 20060831
  • 主分类号: H01L21/4763
  • IPC分类号: H01L21/4763
TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS
摘要:
By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.
信息查询
IPC分类:
H 电学
H01 基本电气元件
H01L 半导体器件;其他类目中不包括的电固体器件(使用半导体器件的测量入G01;一般电阻器入H01C;磁体、电感器、变压器入H01F;一般电容器入H01G;电解型器件入H01G9/00;电池组、蓄电池入H01M;波导管、谐振器或波导型线路入H01P;线路连接器、汇流器入H01R;受激发射器件入H01S;机电谐振器入H03H;扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R;一般电光源入H05B;印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K;在具有特殊应用的电路中使用的半导体器件见应用相关的小类)
H01L21/00 专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02 .半导体器件或其部件的制造或处理
H01L21/04 ..至少具有一个跃变势垒或表面势垒的器件,例如PN结、耗尽层、载体集结层
H01L21/34 ...具有H01L21/06,H01L21/16及H01L21/18各组不包含的或有或无杂质,例如掺杂材料的半导体的器件
H01L21/46 ....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的(在半导体材料上制作电极的入H01L21/44)
H01L21/461 .....改变半导体材料的表面物理特性或形状的,例如腐蚀、抛光、切割
H01L21/4763 ......非绝缘层的沉积,例如绝缘层上的导电层、电阻层;这些层的后处理(电极的制造入H01L21/28)
0/0