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    SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER
    1.
    发明申请
    SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER 审中-公开
    采用拉伸应力覆盖层的替代浇口方法中的超级填充条件

    公开(公告)号：US20120223388A1

    公开(公告)日：2012-09-06

    申请号：US13471818

    申请日：2012-05-15

    申请人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    发明人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823807 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/7843

    摘要： In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

    摘要翻译： 在用于在半导体器件中形成高k金属栅电极的替代栅极方法中，栅极开口的锥形配置可以通过使用横向邻近栅电极结构设置的拉应力电介质材料来实现。 因此，可以实现优异的沉积条件，同时可以有效地将拉伸应力分量用于一种类型的晶体管中的应变工程。 此外，可以在提供替换栅电极结构之后施加附加的压缩应力介电材料。

    SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE
    2.
    发明申请
    SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE 审中-公开
    通过半导体器件的隔离结构封装的自对准接触结构

    公开(公告)号：US20120021581A1

    公开(公告)日：2012-01-26

    申请号：US13237268

    申请日：2011-09-20

    申请人： Thomas Werner ,  Frank Feustel ,  Kai Frohberg

    发明人： Thomas Werner ,  Frank Feustel ,  Kai Frohberg

    IPC分类号： H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28518 ,  H01L21/76232

    摘要： By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements.

    摘要翻译： 通过形成在由有源区的半导体材料限定的高度水平之上延伸的隔离结构，相应的凹槽可以与完成基本晶体管结构的栅电极结构相结合。 这些凹部可以随后用适当的接触材料填充，从而以自对准的方式形成大面积的接触，而不需要层间绝缘材料的沉积和图案化。 此后，例如，可以基于公知的技术形成第一金属化层，其中金属线可以直接连接到相应的“大面积”接触元件。

    MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES
    5.
    发明申请
    MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES 审中-公开
    微结构装置，其中包括在相互间隔的金属线之间具有自对准空气GAPS的金属化结构

    公开(公告)号：US20090294898A1

    公开(公告)日：2009-12-03

    申请号：US12400983

    申请日：2009-03-10

    申请人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    发明人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    IPC分类号： H01L23/58 ,  H01L21/764

    CPC分类号： H01L21/7682 ,  H01L21/76885

    摘要： Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material.

    摘要翻译： 可以通过在金属线附近凹陷介电材料并形成相应的侧壁间隔元件，以自对准的方式提供半空间复杂金属化系统的紧密间隔金属线之间的亚光刻分辨率的气隙。 此后，间隔元件可以用作蚀刻掩模，以便基于相应的气隙限定间隙的横向尺寸，然后可以通过沉积另外的电介质材料来获得。

    TEST STRUCTURE FOR OPC-RELATED SHORTS BETWEEN LINES IN A SEMICONDUCTOR DEVICE
    7.
    发明申请
    TEST STRUCTURE FOR OPC-RELATED SHORTS BETWEEN LINES IN A SEMICONDUCTOR DEVICE 有权
    在半导体器件中的线之间的与OPC相关的短路的测试结构

    公开(公告)号：US20080099761A1

    公开(公告)日：2008-05-01

    申请号：US11747320

    申请日：2007-05-11

    申请人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    发明人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    IPC分类号： H01L21/66 ,  H01L23/58

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： OPC results may be efficiently evaluated on the basis of a test structure containing a plurality of line features with opposing end portions. Thus, for different line parameters, the effect of OPC may be determined for a given critical tip-to-tip distance by determining the leakage behavior of the test assemblies, each having different design parameter values for line width and lateral distance between adjacent lines.

    摘要翻译： 可以基于包含具有相对端部的多个线特征的测试结构来有效地评估OPC结果。 因此，对于不同的线路参数，可以通过确定测试组件的泄漏行为来确定给定的临界尖端到尖端距离的OPC的效果，每个测试组件对于线宽和相邻线之间的横向距离具有不同的设计参数值。

    METHOD OF FORMING AN ETCH INDICATOR LAYER FOR REDUCING ETCH NON-UNIFORMITIES
    8.
    发明申请
    METHOD OF FORMING AN ETCH INDICATOR LAYER FOR REDUCING ETCH NON-UNIFORMITIES 有权
    形成蚀刻指示剂层以减少蚀刻非均匀性的方法

    公开(公告)号：US20080026487A1

    公开(公告)日：2008-01-31

    申请号：US11688280

    申请日：2007-03-20

    申请人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    发明人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    IPC分类号： H01L21/02

    CPC分类号： H01L21/31144 ,  H01L21/26506 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76825 ,  H01L22/26 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advantageously, the material may be incorporated by ion implantation which provides reduced non-uniformity compared to etch non-uniformities, while the implantation process provides the potential for introducing even very “exotic” implantation species. In some embodiments, the substrate-to-substrate uniformity of the patterning of dual damascene structures may be increased.

    摘要翻译： 通过在形成待图案化的材料层之后并入蚀刻控制材料，可以使用具有高度显着的辐射波长的适当材料来在蚀刻工艺期间产生独特的端点检测信号。 有利地，该材料可以通过离子注入并入，与蚀刻非均匀性相比，其提供了降低的不均匀性，而植入工艺提供了引入甚至非常“异乎寻常”的植入物种的潜力。 在一些实施例中，可以增加双镶嵌结构的图案化的基板到基板的均匀性。