发明申请
US20080077647A1 Parameterized VLSI Architecture And Method For Binary Multipliers 审中-公开
二进制乘数的参数化VLSI架构和方法

  • 专利标题: Parameterized VLSI Architecture And Method For Binary Multipliers
  • 专利标题(中): 二进制乘数的参数化VLSI架构和方法
  • 申请号: US11850887
    申请日: 2007-09-06
  • 公开(公告)号: US20080077647A1
    公开(公告)日: 2008-03-27
  • 发明人: Adly FamThomas Poonnen
  • 申请人: Adly FamThomas Poonnen
  • 主分类号: G06F7/487
  • IPC分类号: G06F7/487
Parameterized VLSI Architecture And Method For Binary Multipliers
摘要:
Systems and methods of multiplying binary numbers are disclosed. In one such system there is a Sigma unit and an Omega unit. The Sigma unit may generate partial sums of the multiplier and shifted forms of the multiplier. The Omega unit may have a plurality of control units, a plurality of switch units, and a multi-shifter-adder (“MSA”). In some embodiments of the invention, more than one Omega unit is provided.
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