Parameterized VLSI Architecture And Method For Binary Multipliers
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    发明申请
    Parameterized VLSI Architecture And Method For Binary Multipliers 审中-公开
    二进制乘数的参数化VLSI架构和方法

    公开(公告)号:US20080077647A1

    公开(公告)日:2008-03-27

    申请号:US11850887

    申请日:2007-09-06

    IPC分类号: G06F7/487

    CPC分类号: G06F7/5324

    摘要: Systems and methods of multiplying binary numbers are disclosed. In one such system there is a Sigma unit and an Omega unit. The Sigma unit may generate partial sums of the multiplier and shifted forms of the multiplier. The Omega unit may have a plurality of control units, a plurality of switch units, and a multi-shifter-adder (“MSA”). In some embodiments of the invention, more than one Omega unit is provided.

    摘要翻译: 公开了二进制数乘法的系统和方法。 在一个这样的系统中有一个Sigma单位和一个欧米茄单位。 Sigma单位可以产生乘数的部分和和乘法器的移位形式。 Omega单元可以具有多个控制单元,多个开关单元和多移位加法器(“MSA”)。 在本发明的一些实施例中,提供了多于一个的Omega单元。