Invention Application
- Patent Title: COMPLEMENTARY MIRROR IMAGE EMBEDDED PLANAR RESISTOR ARCHITECTURE
- Patent Title (中): 补充镜像图像嵌入式平面电阻结构
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Application No.: US11861297Application Date: 2007-09-26
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Publication No.: US20080093113A1Publication Date: 2008-04-24
- Inventor: Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
- Applicant: Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
- Applicant Address: TW Hsinchu
- Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Current Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Current Assignee Address: TW Hsinchu
- Priority: TW95138693 20061020
- Main IPC: H05K1/16
- IPC: H05K1/16

Abstract:
A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.
Public/Granted literature
- US08035036B2 Complementary mirror image embedded planar resistor architecture Public/Granted day:2011-10-11
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