发明申请
US20080104332A1 CACHE MEMORY SYSTEM AND METHOD FOR PROVIDING TRANSACTIONAL MEMORY 有权
用于提供交易记忆的高速缓存存储器系统和方法

  • 专利标题: CACHE MEMORY SYSTEM AND METHOD FOR PROVIDING TRANSACTIONAL MEMORY
  • 专利标题(中): 用于提供交易记忆的高速缓存存储器系统和方法
  • 申请号: US11554672
    申请日: 2006-10-31
  • 公开(公告)号: US20080104332A1
    公开(公告)日: 2008-05-01
  • 发明人: Blaine D. GaitherJudson E. Veazey
  • 申请人: Blaine D. GaitherJudson E. Veazey
  • 主分类号: G06F13/28
  • IPC分类号: G06F13/28
CACHE MEMORY SYSTEM AND METHOD FOR PROVIDING TRANSACTIONAL MEMORY
摘要:
A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an owned state, an exclusive state, a shared state, and an invalid state. Upon initiation of a transaction accessing at least one of the cache lines, each of the lines is ensured to be either shared or invalid. During the transaction, in response to an external request for any cache line in the modified, owned, or exclusive state, each line in the modified or owned state is invalidated without writing the line to a main memory. Also, each exclusive line is demoted to either the shared or invalid state, and the transaction is aborted.
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