公开(公告)号：US08473686B2

公开(公告)日：2013-06-25

申请号：US13464962

申请日：2012-05-05

申请人： Blaine D Gaither

发明人： Blaine D Gaither

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/082 ,  G06F12/128

摘要： Methods for selecting a line to evict from a data storage system are provided. A computer system implementing a method for selecting a line to evict from a data storage system is also provided. The methods include selecting an uncached class line for eviction prior to selecting a cached class line for eviction.

公开(公告)号：US20120311267A1

公开(公告)日：2012-12-06

申请号：US13149493

申请日：2011-05-31

申请人： Blaine D. Gaither ,  David A. Plettner

发明人： Blaine D. Gaither ,  David A. Plettner

IPC分类号： G06F12/08

CPC分类号： G06F12/128 ,  G06F12/0802 ,  G06F12/12

摘要： A processor transmits clean castout messages indicating that a cache line is not dirty and is no longer being stored by a lowest level cache of the processor. An external cache receives the clean castout messages and manages cache lines based in part on the clean castout messages.

摘要翻译： 一个处理器传输清除的丢弃消息，指示高速缓存行不脏，并且不再由处理器的最低级缓存存储。 外部缓存部分地基于干净的丢弃消息来接收干净的丢弃消息并管理高速缓存行。

公开(公告)号：US08176293B2

公开(公告)日：2012-05-08

申请号：US12383766

申请日：2009-03-27

申请人： Blaine D. Gaither ,  John A. Morrison

发明人： Blaine D. Gaither ,  John A. Morrison

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G06F9/455

CPC分类号： G06F9/4856 ,  G06F9/45558 ,  G06F2009/4557

摘要： Embodiments of the present invention are directed to enhancing VPAR monitors to allow an active VPAR to be moved from one machine to another, as well as to enhancing virtual-machine monitors to move active VPARs from one machine to another. Because traditional VPAR monitors lack access to many computational resources and to executing-operating-system state, VPAR movement is carried out primarily by specialized routines executing within active VPARs, unlike the movement of guest operating systems between machines carried out by virtual-machine-monitor routines.

摘要翻译： 本发明的实施例涉及增强VPAR监视器以允许主动VPAR从一个机器移动到另一个机器，以及增强虚拟机监视器以将活动VPAR从一个机器移动到另一个机器。 由于传统的VPAR监视器无法访问许多计算资源和执行操作系统状态，VPAR运动主要是通过在主动VPAR内执行的专门程序进行的，这与虚拟机监视器执行的机器之间的客户操作系统的移动不同 例程。

公开(公告)号：US20100235562A1

公开(公告)日：2010-09-16

申请号：US12403712

申请日：2009-03-13

申请人： Blaine D. Gaither ,  Andrew R. Wheeler

发明人： Blaine D. Gaither ,  Andrew R. Wheeler

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7201

摘要： A switch module having shared memory that is allocated to other blade servers. A memory controller partitions and enables access to partitions of the shared memory by requesting blade servers.

摘要翻译： 具有分配给其他刀片服务器的共享存储器的交换机模块。 内存控制器通过请求刀片服务器来分区并启用对共享内存分区的访问。

公开(公告)号：US20090210628A1

公开(公告)日：2009-08-20

申请号：US12194687

申请日：2008-08-20

申请人： Blaine D. Gaither

发明人： Blaine D. Gaither

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/082 ,  G06F12/128

摘要： Methods for selecting a line to evict from a data storage system are provided. A computer system implementing a method for selecting a line to evict from a data storage system is also provided. The methods include selecting an uncached class line for eviction prior to selecting a cached class line for eviction.

摘要翻译： 提供了从数据存储系统中选择要排除的行的方法。 还提供了一种实现用于从数据存储系统中选择要排出的行的方法的计算机系统。 这些方法包括在选择一个缓存的等级线进行驱逐之前，选择一个未被缓存的类别线。

公开(公告)号：US20080104329A1

公开(公告)日：2008-05-01

申请号：US11554827

申请日：2006-10-31

申请人： Blaine D. Gaither ,  Patrick Knebel

发明人： Blaine D. Gaither ,  Patrick Knebel

IPC分类号： G06F12/00

CPC分类号： G06F12/0888 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0897

摘要： A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.

摘要翻译： 提供了用于将处理器与主存储器可操作地耦合的高速缓存。 高速缓存包括与高速缓冲存储器可操作地耦合的高速缓冲存储器和高速缓存控制器。 缓存控制器被配置为接收由高速缓冲存储器或主存储器满足的存储器请求。 此外，高速缓存控制器被配置为处理高速缓存活动信息以使至少一个存储器请求绕过高速缓冲存储器。

公开(公告)号：US06889244B1

公开(公告)日：2005-05-03

申请号：US09703427

申请日：2000-10-31

申请人： Blaine D. Gaither ,  Bret A. McKee

发明人： Blaine D. Gaither ,  Bret A. McKee

IPC分类号： G06F15/16 ,  H04L29/08

CPC分类号： H04L67/1097 ,  G06F9/54 ,  H04L67/303

摘要： A method and apparatus pass messages between server and client applications using a fault tolerant storage system (FTSS). The interconnection fabric that couples the FTSS to the computer systems that host the client and server applications may also be used to carry messages. A networked system capable of hosting a distributed application includes a plurality of computer systems coupled to an FTSS via an FTSS interconnection fabric. The FTSS not only processes file-related I/O transactions, but also includes several message agents to facilitate message transfer in a reliable and fault tolerant manner. The message agents include a conversational communication agent, an event-based communication agent, a queue-based communication agent, a request/reply communication agent, and an unsolicited communication agent. The highly reliable and fault tolerant nature of the FTSS ensures that the FTSS can guarantee delivery of a message transmitted from a sending computer system to a destination computer system. As soon as a message is received by the FTSS from a sending computer system, the message is committed to a nonvolatile fault tolerant write cache. Thereafter, the message is written to a redundant array of independent disks (RAID) of the FTSS, and processed by one of the message agents.

摘要翻译： 一种方法和设备使用容错存储系统（FTSS）在服务器和客户端应用程序之间传递消息。 将FTSS耦合到托管客户端和服务器应用程序的计算机系统的互连结构也可以用于携带消息。 能够托管分布式应用的联网系统包括经由FTSS互连结构耦合到FTSS的多个计算机系统。 FTSS不仅处理文件相关的I / O事务，还包括几个消息代理，以便以可靠和容错的方式促进消息传输。 消息代理包括会话通信代理，基于事件的通信代理，基于队列的通信代理，请求/应答通信代理和未经请求的通信代理。 FTSS的高度可靠和容错的性质确保了FTSS可以保证从发送计算机系统传送到目标计算机系统的消息的传送。 一旦FTSS从发送计算机系统接收到消息，该消息被提交到非易失性容错写缓存。 此后，消息被写入FTSS的独立磁盘（RAID）的冗余阵列，并由消息代理之一处理。

公开(公告)号：US06813691B2

公开(公告)日：2004-11-02

申请号：US10001584

申请日：2001-10-31

申请人： Blaine D. Gaither ,  Benjamin D. Osecky

发明人： Blaine D. Gaither ,  Benjamin D. Osecky

IPC分类号： G06F1200

CPC分类号： G06F12/0804 ,  G06F12/0831 ,  G06F12/0897 ,  Y10S707/99932

摘要： A cache system improves performance by limiting the number of dirty entries in a cache. The cache system may be further improve performance by limiting the number of dirty entries in a cache that might be subject to a cache-to-cache transfer. In a first example, a cache system counts the total number of dirty entries in the cache and preemptively evicts at least one dirty entry when the count exceeds a predetermined threshold. In a variation, a cache system counts dirty cache entries that result from a cache-to-cache transfer, and evicts at least one dirty entry that results from a cache-to-cache transfer when the number exceeds a predetermined threshold. For either system, the predetermined threshold may be dynamically varied to determine a value that optimizes performance.

摘要翻译： 缓存系统通过限制高速缓存中脏条目的数量来提高性能。 缓存系统可以通过限制高速缓存中可能受到高速缓存到高速缓存传输的脏条目的数量来进一步提高性能。 在第一示例中，高速缓存系统对高速缓存中的脏条目的总数进行计数，并且当计数超过预定阈值时，预先将至少一个脏条目排除。 在一个变型中，缓存系统计算由高速缓存到高速缓存传输所产生的脏缓存条目，并且当数量超过预定阈值时，将至少一个由高速缓存到高速缓存传输产生的脏条目驱逐出去。 对于任一系统，可以动态地改变预定阈值以确定优化性能的值。

公开(公告)号：US4453212A

公开(公告)日：1984-06-05

申请号：US282919

申请日：1981-07-13

申请人： Blaine D. Gaither ,  William W. Farley, IV ,  Albert Johnson ,  Brian L. Parker

发明人： Blaine D. Gaither ,  William W. Farley, IV ,  Albert Johnson ,  Brian L. Parker

IPC分类号： G06F9/34 ,  G06F9/355 ,  G06F12/02 ,  G06F12/10 ,  G06F13/00 ,  G06F7/00 ,  G06F9/00

CPC分类号： G06F9/342

摘要： Address generating apparatus which uses narrow data paths for generating a wide logical address and which also provides for programs to access very large shared data structures outside their normally available addressing range and over an extended range of addresses. Selective indexed addressing is employed for providing index data which is also used for deriving variable dimension override data. During address generation, selected index data is added to a displacement provided by an instruction for deriving a dimension override value as well as an offset. The derived dimension override value is used to selectively access an address locating entry in a table of entries corresponding to the applicable program. The resulting accessed address locating entry is in turn used to determine the particular portion of memory against which the offset is to be applied.

摘要翻译： 地址生成装置，其使用窄数据路径来生成广泛的逻辑地址，并且还提供用于访问非常大的共享数据结构之外的程序以在其通常可用的寻址范围之外以及扩展的地址范围。 选择索引寻址用于提供索引数据，其也用于导出可变维度覆盖数据。 在地址生成期间，将所选择的索引数据添加到由用于导出维度超越值以及偏移的指令所提供的位移。 导出的维度覆盖值用于选择性地访问与适用程序相对应的条目表中的地址定位条目。 结果访问的地址定位条目又被用于确定要应用偏移的存储器的特定部分。

公开(公告)号：US09910808B2

公开(公告)日：2018-03-06

申请号：US14389910

申请日：2012-04-30

申请人： Blaine D. Gaither ,  Robert J. Brooks ,  Benjamin D. Osecky ,  Kathryn A. Evertson ,  Andrew R. Wheeler ,  David Fisk

发明人： Blaine D. Gaither ,  Robert J. Brooks ,  Benjamin D. Osecky ,  Kathryn A. Evertson ,  Andrew R. Wheeler ,  David Fisk

IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F17/30 ,  G06F13/14 ,  G06F12/02 ,  G06F11/16

CPC分类号： G06F13/4027 ,  G06F11/1666 ,  G06F12/0284 ,  G06F13/16 ,  G06F13/1652 ,  G06F13/404 ,  G06F17/30368

摘要： In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.