In response to a request from a central processing unit (CPU) 11 (i.e., firmware) of a node 10, a transfer control unit 14a of a direct memory access (DMA) controller 14 transmits a message and data to another discretionary node 3 by way of a serial bus 1, a switch 2 or the like. In this event, the firmware stores data to be transmitted, a message, and a descriptor thereof in memory 12. In the case of requesting the transmission of the message, the descriptor contains a flag indicating “whether or not there is a need to wait for a response from the data transmission destination”. If the flag is set to ON, the transfer control unit 14a notifies the firmware of a simulated completion immediately instead of waiting for a completion response from the transmission destination node 3.