发明申请
US20080116496A1 Integrating a DRAM with an SRAM having butted contacts and resulting devices
审中-公开
将DRAM与具有对接触点和所产生的器件的SRAM集成
- 专利标题: Integrating a DRAM with an SRAM having butted contacts and resulting devices
- 专利标题(中): 将DRAM与具有对接触点和所产生的器件的SRAM集成
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申请号: US11809642申请日: 2007-06-01
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公开(公告)号: US20080116496A1公开(公告)日: 2008-05-22
- 发明人: Kuo-Chyuan Tzeng , Kuo-Chiang Ting , Chen-Jong Wang , Min-Hsiung Chiang , Chih-Yang Pai
- 申请人: Kuo-Chyuan Tzeng , Kuo-Chiang Ting , Chen-Jong Wang , Min-Hsiung Chiang , Chih-Yang Pai
- 主分类号: H01L27/108
- IPC分类号: H01L27/108
摘要:
A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.