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    Integrating a DRAM with an SRAM having butted contacts and resulting devices
    1.
    发明申请
    Integrating a DRAM with an SRAM having butted contacts and resulting devices 审中-公开
    将DRAM与具有对接触点和所产生的器件的SRAM集成

    公开(公告)号：US20080116496A1

    公开(公告)日：2008-05-22

    申请号：US11809642

    申请日：2007-06-01

    申请人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

    发明人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

    IPC分类号： H01L27/108

    CPC分类号： H01L27/105 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116

    摘要： A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.

    摘要翻译： 提供了一种新颖的SOC结构及其制造方法。 SOC包括逻辑区域，SRRM和DRAM区域。 金属 - 绝缘体 - 金属）构造中的DRAM单元中的存储电容器形成在第一介电层中，具有大的垂直表面积。 形成在所述第一电介质层中的对接触点包括邻接SRAM单元中的第一和第二导电区域的底部以及耦合到第一金属层的垂直对齐的顶部。 顶部具有比底部大的深度大得多的深度，而其尺寸基本上更小。 形成这种SOC结构不需要在现有的CMOS制造工艺上增加复杂的，容易出错的附加处理步骤，因此对整个SOC产品产量几乎没有影响。

    Dual poly layer and method of manufacture
    3.
    发明授权
    Dual poly layer and method of manufacture 有权
    双层多层及其制造方法

    公开(公告)号：US07208369B2

    公开(公告)日：2007-04-24

    申请号：US10662609

    申请日：2003-09-15

    申请人： Chih-Yang Pai ,  Min-Hsiung Chiang ,  Chen-Jong Wang ,  Shou-Gwo Wuu

    发明人： Chih-Yang Pai ,  Min-Hsiung Chiang ,  Chen-Jong Wang ,  Shou-Gwo Wuu

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  Y10S257/903 ,  Y10S257/904

    摘要： Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.

    摘要翻译： 提供了具有双重多晶硅电极的半导体器件和制造方法。 半导体器件包括沉积在第二多晶硅层上的第一多晶硅层。 每个多晶硅层可以单独掺杂。 该方法还允许晶片上的一些半导体器件具有单个多晶硅晶片和其它器件以具有双重多晶硅层。 在一个实施例中，半导体器件用于形成存储器件，其中位于单元区域中的存储电容器和晶体管形成双重多晶硅层，并且外围区域中的器件形成有单个多晶硅层。

    Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers
    4.
    发明授权
    Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers 有权
    用于形成具有减少的多晶硅桁架的掩埋堆叠电容器结构的方法

    公开(公告)号：US06613690B1

    公开(公告)日：2003-09-02

    申请号：US10197318

    申请日：2002-07-17

    申请人： Chung-Wei Chang ,  Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Min-Hsiang Chiang ,  Chi-Hsing Lo

    发明人： Chung-Wei Chang ,  Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Min-Hsiang Chiang ,  Chi-Hsing Lo

    IPC分类号： H01L21302

    CPC分类号： H01L27/1087 ,  H01L21/32139 ,  H01L27/10835 ,  H01L28/91

    摘要： A process for forming a buried stack capacitor structure in a recessed region of a shallow trench isolation (STI) region, has been developed. The process features a unique sequence of procedures eliminating possible polysilicon stringers or residuals which if left remaining would result in leakage or shorts between conductive elements. The unique sequence of procedures include: deposition of a silicon oxide layer on the polysilicon layer from which the storage node structure will be defined from; photoresist plugs used to protect the portions of the silicon oxide and the underlying polysilicon layer located in the recessed region, during definition of the polysilicon storage node structure; and definition of the polysilicon storage node structure via a wet etch procedure, using the silicon oxide layer for protection of the underlying polysilicon storage node structure.

    摘要翻译： 已经开发了在浅沟槽隔离（STI）区域的凹陷区域中形成掩埋堆叠电容器结构的工艺。 该方法具有唯一的程序序列，可以消除可能的多晶硅桁条或残余物，如果留下剩余物会导致导电元件之间的泄漏或短路。 独特的程序顺序包括：在多晶硅层上沉积氧化硅层，从其上定义存储节点结构; 用于在多晶硅存储节点结构的定义期间用于保护位于凹陷区域中的氧化硅部分和下面的多晶硅层的光阻胶塞; 以及通过湿蚀刻程序定义多晶硅存储节点结构，使用氧化硅层来保护下面的多晶硅存储节点结构。

    Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers
    8.
    发明授权
    Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers 有权
    在最厚的金属间介电层内制造金属绝缘体金属（MIM）电容器的方法

    公开(公告)号：US08716100B2

    公开(公告)日：2014-05-06

    申请号：US13212922

    申请日：2011-08-18

    申请人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

    发明人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

    IPC分类号： H01L21/20

    CPC分类号： H01L28/86 ,  H01L23/5223 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

    摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。 可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。 诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。 厚IMD层上方的金属层可以用作顶部电极连接。 厚IMD层下面的金属层可以用作底部电极连接。 电容器可以是不同的形状，例如圆柱形或凹形。 可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

    Metal-Insulator-Metal Capacitor and Method of Fabricating
    9.
    发明申请
    Metal-Insulator-Metal Capacitor and Method of Fabricating 有权
    金属绝缘体 - 金属电容器和制造方法

    公开(公告)号：US20130043560A1

    公开(公告)日：2013-02-21

    申请号：US13212922

    申请日：2011-08-18

    申请人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

    发明人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L28/86 ,  H01L23/5223 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

    摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。 可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。 诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。 厚IMD层上方的金属层可以用作顶部电极连接。 厚IMD层下面的金属层可以用作底部电极连接。 电容器可以是不同的形状，例如圆柱形或凹形。 可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

    Single transistor random access memory (1T-RAM) cell with dual threshold voltages
    10.
    发明授权
    Single transistor random access memory (1T-RAM) cell with dual threshold voltages 有权
    具有双阈值电压的单晶体管随机存取存储器（1T-RAM）单元

    公开(公告)号：US06670664B1

    公开(公告)日：2003-12-30

    申请号：US10279809

    申请日：2002-10-22

    申请人： Kuo-Chyuan Tzeng ,  Dennis J. Sinitsky ,  Chen-Jong Wang ,  Wen-Chaun Chiang

    发明人： Kuo-Chyuan Tzeng ,  Dennis J. Sinitsky ,  Chen-Jong Wang ,  Wen-Chaun Chiang

    IPC分类号： H01L27108

    CPC分类号： H01L27/10805 ,  H01L27/10873

    摘要： A random access memory cell and a method for fabrication thereof provide a field effect transistor device laterally adjoining a metal oxide semiconductor capacitor device, each formed within an active region of a semiconductor substrate. Within the random access memory cell and method: (1) a single fluorinated silicon oxide layer of a single thickness serves as both a gate dielectric layer within the field effect transistor device and a capacitor dielectric layer within the metal oxide semiconductor capacitor device; and (2) a channel region within the field effect transistor device has a different threshold voltage adjusting dopant concentration in comparison with a semiconductor plate region within the metal oxide semiconductor capacitor device. The random access memory cell is fabricated with enhanced performance.

    摘要翻译： 随机存取存储单元及其制造方法提供横向邻接金属氧化物半导体电容器器件的场效应晶体管器件，每个形成在半导体衬底的有源区内。 在随机存取存储器单元和方法中：（1）单个厚度的单个氟化硅氧化物层用作场效应晶体管器件内的栅极电介质层和金属氧化物半导体电容器器件内的电容器电介质层; 和（2）场效应晶体管器件内的沟道区域与金属氧化物半导体电容器件内的半导体板区域相比具有不同的阈值电压调整掺杂剂浓度。 该随机存取存储器单元以增强的性能制造。