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US20080150583A1 BUFFER CIRCUIT 有权
缓冲电路

BUFFER CIRCUIT
摘要：
A buffer circuit having an input terminal and an output terminal comprises a first inverter having an input node coupled to the input terminal and an output node coupled to the output terminal, a second inverter having an input node coupled to a reference voltage and an output node, a third inverter having an input node coupled to the output terminal and an output node coupled to the output node of the second inverter, a fourth inverter having an input node coupled to the output node of the second inverter and an output node coupled to the output terminal, a fifth inverter having an input node and an output node coupled to the output terminal, a sixth inverter having an input node and an output node coupled to the output node of the second inverter, a first resistive element is coupled between the output terminal and the input node of the fifth inverter, and a second resistive element is coupled between the output node of the second inverter and the input node of the sixth inverter.
摘要（中）：

具有输入端和输出端的缓冲电路包括具有耦合到输入端的输入节点和耦合到输出端的输出节点的第一反相器，具有耦合到参考电压的输入节点的第二反相器和输出节点 具有耦合到所述输出端的输入节点和耦合到所述第二反相器的输出节点的输出节点的第三反相器，具有耦合到所述第二反相器的输出节点的输入节点的第四反相器和耦合到所述第二反相器的输出节点的输出节点 输出端子，具有输入节点和耦合到输出端子的输出节点的第五反相器，具有耦合到第二反相器的输出节点的输入节点和输出节点的第六反相器，第一电阻元件耦合在输出端 端子和第五反相器的输入节点，第二电阻元件耦合在第二反相器的输出节点和第六反相器的输入节点之间。

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