发明申请
- 专利标题： PACKING BOARD FOR ELECTRONIC DEVICE, PACKING BOARD MANUFACTURING METHOD, SEMICONDUCTOR MODULE, SEMICONDUCTOR MODULE MANUFACTURING METHOD, AND MOBILE DEVICE
- 专利标题（中）： 电子装置用包装板，包装板制造方法，半导体模块，半导体模块制造方法和移动装置
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申请号： US11957030申请日： 2007-12-14
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公开(公告)号： US20080157338A1公开(公告)日： 2008-07-03
- 发明人: Mayumi Nakasato , Kiyoshi Shibata , Yoshio Okayama , Ryosuke Usui , Hideki Mizuhara
- 申请人： Mayumi Nakasato , Kiyoshi Shibata , Yoshio Okayama , Ryosuke Usui , Hideki Mizuhara
- 申请人地址： JP Osaka
- 专利权人： Sanyo Electric Co., Ltd.
- 当前专利权人： Sanyo Electric Co., Ltd.
- 当前专利权人地址： JP Osaka
- 优先权： JP2006-337708 20061215; JP2006-343036 20061220; JP2007-314240 20071205; JP2007-314241 20071205
- 主分类号： H01L21/50
- IPC分类号： H01L21/50 ; H01L23/52
摘要：
A manufacturing technology is provided capable of improving the reliability of a semiconductor module having a via contact connected to an electrode part of a semiconductor device. A conductive bump is formed on an insulating layer such that the end of the conductive bump is in contact with an electrode of a semiconductor substrate. By pressure-molding the assembly using a press machine, the semiconductor substrate, the conductive bump, and the insulating layer are integrated. With this, the conductive bump is allowed to embed itself in the insulating layer while maintaining contact with the electrode. The insulating layer is subject to laser irradiation from above so as to form an aperture exposing the conductive bump. Subsequently, the upper surface of the insulating layer and the interior surface of the aperture are plated with copper by electroless plating and electroplating so as to form a copper plating layer, and a via contact is formed in the aperture so as to coat the inner wall of the aperture.
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