公开(公告)号：US09024446B2

公开(公告)日：2015-05-05

申请号：US13381299

申请日：2010-06-30

申请人： Ryosuke Usui ,  Yusuke Igarashi ,  Yasunori Inoue ,  Mayumi Nakasato ,  Masayuki Nagamatsu ,  Yasuhiro Kohara

发明人： Ryosuke Usui ,  Yusuke Igarashi ,  Yasunori Inoue ,  Mayumi Nakasato ,  Masayuki Nagamatsu ,  Yasuhiro Kohara

IPC分类号： H05K1/00 ,  H05K3/44 ,  H01L23/373 ,  H05K1/05 ,  H05K1/18 ,  H01L23/00

CPC分类号： H05K3/445 ,  H01L23/3735 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H05K1/05 ,  H05K1/053 ,  H05K1/056 ,  H05K1/185 ,  H05K2201/0195 ,  H05K2201/068 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had problems in having low rigidity and a tendency to bend. The ductility of the metal can be obstructed, and the metal protected; by covering substantially the whole area of the front and back sides of the metal core, consisting of metal as the main material, with a first ceramic film and a second ceramic film that obstruct the ductility of the aforementioned metal-core; and covering each of the ceramic films with insulated resin films, to cover the fragility of these ceramics.

摘要翻译： 传统的印刷电路板具有热辐射特性差的问题，并且用于改善热辐射特性的金属芯印刷电路板具有刚性低和弯曲倾向的问题。 金属的延展性可能受到阻碍，金属受到保护; 通过覆盖由金属作为主要材料构成的金属芯的正面和背面的大部分整个面积与第一陶瓷膜和阻碍上述金属芯的延展性的第二陶瓷膜; 并用绝缘树脂膜覆盖每个陶瓷膜，以覆盖这些陶瓷的脆性。

公开(公告)号：US08656581B2

公开(公告)日：2014-02-25

申请号：US12563849

申请日：2009-09-21

申请人： Makoto Murai ,  Yasuhiro Kohara ,  Ryosuke Usui

发明人： Makoto Murai ,  Yasuhiro Kohara ,  Ryosuke Usui

IPC分类号： H05K3/36

CPC分类号： H05K3/243 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/284 ,  H05K3/3452 ,  H05K3/382 ,  H05K2201/0989 ,  H05K2203/049 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49222 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for fabricating a circuit apparatus includes forming a wiring layer, a conductive layer, and a first insulating layer on the wiring substrate, removing the conductive layer in an opening of the first insulating layer so as to expose the wiring layer, forming a gold plating layer on the wiring layer, removing the first insulating layer and the conductive layer, forming a second insulating layer on the wiring substrate, the second insulating layer having an opening through which the gold plating and adjacent wiring layers are exposed, and electrically connecting a circuit element to the gold plating layer.

摘要翻译： 一种制造电路装置的方法，包括在布线基板上形成布线层，导电层和第一绝缘层，去除第一绝缘层的开口中的导电层，以露出布线层，形成金 在所述布线层上除去所述第一绝缘层和所述导电层，在所述布线基板上形成第二绝缘层，所述第二绝缘层具有开金属镀层和相邻配线层露出的开口， 电路元件到镀金层。

公开(公告)号：US20110241203A1

公开(公告)日：2011-10-06

申请号：US13139075

申请日：2009-12-10

申请人： Mayumi Nakasato ,  Katsumi Ito ,  Ryosuke Usui ,  Yusuke Igarashi

发明人： Mayumi Nakasato ,  Katsumi Ito ,  Ryosuke Usui ,  Yusuke Igarashi

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/111 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/09427 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor module includes a device mounting board and a semiconductor device. The semiconductor device and the device mounting board are flip-chip connected to each other, and a device electrode provided in the semiconductor device and a substrate electrode provided in the device mounting board are connected by soldering. In a cross section along a line connecting the adjacent substrate electrodes, the width L1 of the substrate electrode is narrower than the width L2 of the device electrode corresponding to the substrate electrode.

摘要翻译： 半导体模块包括器件安装板和半导体器件。 半导体器件和器件安装板彼此倒装连接，并且设置在半导体器件中的器件电极和设置在器件安装板中的衬底电极通过焊接连接。 在沿着连接相邻的基板电极的线的横截面中，基板电极的宽度L1比对应于基板电极的器件电极的宽度L2窄。

公开(公告)号：US20110074025A1

公开(公告)日：2011-03-31

申请号：US12961171

申请日：2010-12-06

申请人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

发明人： Yasuyuki Yanase ,  Yoshio Okayama ,  Kiyoshi Shibata ,  Yasunori Inoue ,  Hideki Mizuhara ,  Ryosuke Usui ,  Tetsuya Yamamoto ,  Masurao Yoshii

IPC分类号： H01L23/482 ,  H01L23/52

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/94 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

摘要翻译： 在半导体模块中的半导体衬底的安装表面（特别是其外周）上形成用于半导体器件的电极。 为了确保电极之间的大间隙，在电极上形成绝缘层。 还形成有穿过绝缘层并连接到电极的多个凸块，以及与凸块一体形成的重新布线图案。 重新布线图案包括凸起区域和与凸起区域相邻延伸的布线区域。 绝缘层形成为具有在凸起之间的间隔中的凹的上表面，并且重新布线图案的布线区域形成为适合该上表面。 重布线图案的布线区域相对于重新布线图案的凸起区域形成为朝向半导体基板压下。

公开(公告)号：US07907390B2

公开(公告)日：2011-03-15

申请号：US11693316

申请日：2007-03-29

申请人： Shin-ya Nakano ,  Yoh Takano ,  Tetsuro Sawai ,  Ryosuke Usui

发明人： Shin-ya Nakano ,  Yoh Takano ,  Tetsuro Sawai ,  Ryosuke Usui

IPC分类号： H01L23/34 ,  H05K5/00 ,  H05K7/00

CPC分类号： H01L23/142 ,  H01L23/3737 ,  H01L23/467 ,  H01L23/498 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0203 ,  H05K1/0265 ,  H05K3/06 ,  H05K3/202 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/10969 ,  H05K2203/0369 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A circuit device includes a metal substrate; and a plurality of circuit elements, mounted on the metal substrate, which electrically connects to the metal substrate. The metal substrate is made of a copper plate of high thermal conductivity. The metal substrate is demarcated into a plurality of sections by insulating films added with a filler for enhancing the thermal conductivity in resin. The circuit elements, which have respective independent operating potentials on a side of the metal substrate of the circuit elements, are respectively provided on separated copper plates.

摘要翻译： 电路装置包括金属基板; 以及多个电路元件，安装在与金属基板电连接的金属基板上。 金属基板由具有高导热性的铜板制成。 通过添加有填充剂的绝缘膜将金属基板划分为多个部分，以提高树脂中的导热性。 在电路元件的金属基板的一侧具有各自的独立工作电位的电路元件分别设置在分离的铜板上。

公开(公告)号：US07875980B2

公开(公告)日：2011-01-25

申请号：US11215121

申请日：2005-08-31

申请人： Toshikazu Imaoka ,  Ryosuke Usui

发明人： Toshikazu Imaoka ,  Ryosuke Usui

IPC分类号： H01L23/12

CPC分类号： H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/183 ,  H05K1/185 ,  H05K3/284 ,  H05K3/4644 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A technique for reducing the size of a semiconductor device is provided. A semiconductor device comprises a base, a semiconductor chip, a chip component, an insulating base, a wiring pattern, a via plug, an external lead-out electrode, a recess, and a resin. The insulating base has a multi-layer structure formed by laminating a plurality of insulator films. The semiconductor chip and the chip component are mounted on the base and embedded in the insulating base. A recess is formed on the surface of the semiconductor device and reaches down to any of wiring conductor layers. The semiconductor chip and the chip component are mounted on the recess.

摘要翻译： 提供了一种用于减小半导体器件的尺寸的技术。 半导体器件包括基底，半导体芯片，芯片部件，绝缘基底，布线图案，通孔塞，外部引出电极，凹部和树脂。 绝缘基底具有通过层叠多个绝缘膜形成的多层结构。 半导体芯片和芯片组件安装在基座上并嵌入绝缘基座中。 在半导体器件的表面上形成凹部，并且到达布线导体层中的任何一个。 半导体芯片和芯片组件安装在凹槽上。

公开(公告)号：US07854062B2

公开(公告)日：2010-12-21

申请号：US12352372

申请日：2009-01-12

申请人： Ryosuke Usui ,  Hideki Mizuhara ,  Yusuke Igarashi ,  Nobuhisa Takakusaki ,  Takeshi Nakamura

发明人： Ryosuke Usui ,  Hideki Mizuhara ,  Yusuke Igarashi ,  Nobuhisa Takakusaki ,  Takeshi Nakamura

IPC分类号： H01K3/10

CPC分类号： H01L21/486 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L24/73 ,  H01L24/97 ,  H01L25/16 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/0035 ,  H05K3/284 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4647 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.

摘要翻译： 本发明提供一种适于通过绝缘层将多层叠布线层彼此连接的电路装置的制造方法。 在本发明的混合集成电路器件的制造方法中，通过在第一绝缘层上层叠第一导电膜，对第一导电膜进行图案化，形成第一绞合层。 在第一布线层中，形成沿厚度方向突出的第一连接部。 此外，包括第一连接部的第一布线层被第二绝缘层覆盖。 第二绝缘层由第一树脂膜和第二树脂膜形成。 第二树脂膜比第一树脂膜含有更少的无机填料。 因此，具有可以容易地形成通孔的优点。

公开(公告)号：US20100264552A1

公开(公告)日：2010-10-21

申请号：US12673409

申请日：2008-08-08

申请人： Mayumi Nakasato ,  Ryosuke Usui ,  Yasunori Inoue ,  Kiyoshi Shibata

发明人： Mayumi Nakasato ,  Ryosuke Usui ,  Yasunori Inoue ,  Kiyoshi Shibata

IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L21/56 ,  H05K1/00 ,  H05K1/11

CPC分类号： H01L23/145 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L29/0657 ,  H01L2221/68345 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/002 ,  H05K3/305 ,  H05K3/4007 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1152 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2224/05599

摘要： A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.

摘要翻译： 电路装置包括：绝缘基体，设置有与纤维填料混合的树脂层，设置在绝缘基底中的凸起，用作连接用电极，倒装芯片安装的半导体器件，以及填充半导体之间的间隙的底部填充物 设备和绝缘基座。 通过使通过树脂层的上表面突出的纤维状填料与底部填充剂接触，提高了底部填充剂和绝缘基材之间的粘合强度。

公开(公告)号：US20100207270A1

公开(公告)日：2010-08-19

申请号：US12679595

申请日：2008-09-25

申请人： Yasuyuki Yanase ,  Yoshio Okayama ,  Ryosuke Usui

发明人： Yasuyuki Yanase ,  Yoshio Okayama ,  Ryosuke Usui

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2924/00

摘要： A semiconductor module is of a structure such that a wiring layer, an insulating resin layer and a semiconductor device are stacked in this order by bonding them together with compression. In the wiring layer, bump electrodes each having a base and a tip portion are provided in positions corresponding respectively to device electrodes of the semiconductor device. The bump electrodes penetrate the insulating resin layer and are electrically coupled to the corresponding device electrodes.

摘要翻译： 半导体模块具有这样的结构，使得布线层，绝缘树脂层和半导体器件通过将它们压缩在一起而依次堆叠。 在布线层中，各自具有基底和尖端部分的凸起电极设置在分别对应于半导体器件的器件电极的位置。 凸块电极穿透绝缘树脂层并电耦合到相应的器件电极。

公开(公告)号：US20090321119A1

公开(公告)日：2009-12-31

申请号：US12495028

申请日：2009-06-30

申请人： Yasuhiro Kohara ,  Ryosuke Usui ,  Yasunori Inoue

发明人： Yasuhiro Kohara ,  Ryosuke Usui ,  Yasunori Inoue

IPC分类号： H05K1/18 ,  H05K1/11

CPC分类号： H05K3/4652 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/0313 ,  H05K3/0029 ,  H05K3/0041 ,  H05K3/386 ,  H05K3/426 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0195 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2203/0554 ,  H01L2924/00014

摘要： A device mounting board is provided with: a substrate structural unit including a substrate made of a composition containing amorphous silicon, a first adhesive layer provided on one of the main surfaces of the substrate, and a second adhesive layer provided on the other main surface of the substrate; a first wiring layer provided on the main surface of the first adhesive layer on the opposite side from the substrate; a second wiring layer provided on the main surface of the second adhesive layer on the opposite side from the substrate; and a via conductor, which is provided in a via hole that penetrates the substrate, the first adhesive layer, and the second adhesive layer, which electrically connects the first wiring layer and the second wiring layer.

摘要翻译： 一种器件安装板设置有：衬底结构单元，包括由包含非晶硅的组合物制成的衬底，设置在衬底的一个主表面上的第一粘合层和设置在衬底的另一个主表面上的第二粘合层 基材; 第一布线层，设置在与基板相反一侧的第一粘合剂层的主表面上; 第二布线层，设置在所述第二粘合层的与所述基板相反的一侧的所述主表面上; 以及通孔导体，其设置在贯通基板的通孔中，第一粘合层和第二粘合层，其电连接第一布线层和第二布线层。