In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.