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1.发明授权Rank select operation between an XIO interface and a double data rate interface 失效XIO接口和双数据速率接口之间的等级选择操作公开(公告)号：US07840744B2
公开(公告)日：2010-11-23
申请号：US11668725
申请日：2007-01-30
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.
摘要翻译： 在一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）生成不指示由第一命令指定的存储器的等级的第一类型的第一命令和相关联的地址; （2）确定存储器是否包括多个等级; （3）如果所述存储器包括多个等级，则使用所述处理器来更新与所述第一命令相关联的地址以指示由所述第一命令所针对的存储器级; （4）如果存储器不包括多个等级，则使用处理器来更新与第一命令相关联的地址以指示存储器不包括多个等级; 和（5）将第一命令和相关联的更新地址转换为用于访问存储器的第二命令和相关联的地址。 提供了许多其他方面。
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2.发明申请Rank Select Operation Between an XIO Interface and a Double Data Rate Interface 失效等级选择XIO接口和双数据速率接口之间的操作公开(公告)号：US20080183985A1
公开(公告)日：2008-07-31
申请号：US11668725
申请日：2007-01-30
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.
摘要翻译： 在一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）生成不指示由第一命令指定的存储器的等级的第一类型的第一命令和相关联的地址; （2）确定存储器是否包括多个等级; （3）如果所述存储器包括多个等级，则使用所述处理器来更新与所述第一命令相关联的地址以指示由所述第一命令所针对的存储器级; （4）如果存储器不包括多个等级，则使用处理器来更新与第一命令相关联的地址以指示存储器不包括多个等级; 和（5）将第一命令和相关联的更新地址转换为用于访问存储器的第二命令和相关联的地址。 提供了许多其他方面。
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3.发明申请Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate Memory 审中-公开使用极限数据速率存储器命令来刷新和刷新双倍数据速率存储器公开(公告)号：US20080183916A1
公开(公告)日：2008-07-31
申请号：US11668531
申请日：2007-01-30
申请人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Ryan Abel Heckendorf , John David Irish , David Alan Norgaard , Ibrahim Abdel-Rahman Ouda , Tolga Ozguner
IPC分类号： G06F13/00
CPC分类号： G06F11/106
摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供适于发出符合第一协议的命令的处理器; （2）提供耦合到所述处理器的存储器，并且可通过符合第二协议的命令来访问; （3）采用符合第二协议的多个擦除命令来检查存储器的相应部分的错误，其中符合第二协议的每个擦除命令是符合由处理器发出的第一协议的擦除命令的转换版本 并且各部分是非顺序的; 和（4）在预定时间段内刷新存储在整个存储器中的位。 提供了许多其他方面。
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4.发明申请Methods and Apparatus for Software Control of a Non-Functional Operation on Memory 审中-公开用于存储器中非功能操作的软件控制的方法和装置公开(公告)号：US20080168262A1
公开(公告)日：2008-07-10
申请号：US11620117
申请日：2007-01-05
申请人： Mark David Bellows , John David Irish , David Alan Norgaard , Tolga Ozguner , Dorothy Marie Thelen
发明人： Mark David Bellows , John David Irish , David Alan Norgaard , Tolga Ozguner , Dorothy Marie Thelen
IPC分类号： G06F9/312
CPC分类号： G06F9/3004
摘要： In a first aspect, a first method of controlling a non-functional operation on a memory of a computer system using software is provided. The first method includes the steps of (1) employing a processor to write bits of data to at least one register external to the processor, wherein the bits of data serve as control bits for the memory; and (2) applying the bits of data to respective pins of the memory so as to cause the non-functional operation to be performed on the memory. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种使用软件来控制计算机系统的存储器上的非功能操作的第一方法。 第一种方法包括以下步骤：（1）使用处理器将数据位写入到处理器外部的至少一个寄存器，其中数据位用作存储器的控制位; 以及（2）将数据位施加到存储器的相应引脚，以使得对存储器执行非功能性操作。 提供了许多其他方面。
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公开(公告)号：US07660908B2
公开(公告)日：2010-02-09
申请号：US10427886
申请日：2003-05-01
IPC分类号： G06F15/167 , G06F15/173 , G06F12/00
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/901 , H04L69/12
摘要： A method, apparatus and computer program product are provided for implementing virtual packet storage via packet work area (PWA) in a network processor system. A mapping area including a packet work area and a corresponding set of packet segment registers (PSRs) are provided. A PSR is loaded with a Packet ID (PID) and a packet translation unit maps the packet data into the corresponding PWA. The PWA address defining an offset into the packet is translated into a physical address. The packet translation unit redirects loads and stores of the PWA into the correct data buffer or buffers in system memory. Packets include one or more data buffers that are chained together, using a buffer descriptor providing the packet physical address. The buffer descriptor points to a data buffer for the packet and to a next buffer descriptor.
摘要翻译： 提供了一种用于通过网络处理器系统中的分组工作区（PWA）实现虚拟分组存储的方法，装置和计算机程序产品。 提供了包括分组工作区域和相应的分组段寄存器（PSR）集合的映射区域。 PSR装载有分组ID（PID），分组转换单元将分组数据映射到对应的PWA中。 定义到分组中的偏移的PWA地址被转换成物理地址。 分组转换单元将PWA的加载和存储重定向到系统存储器中的正确的数据缓冲器或缓冲器。 数据包包括使用提供数据包物理地址的缓冲区描述符链接在一起的一个或多个数据缓冲区。 缓冲区描述符指向数据包的数据缓冲区和下一个缓冲区描述符。
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6.发明授权Method and apparatus for implementing packet command instructions for network processing 失效用于实现网络处理的分组命令指令的方法和装置公开(公告)号：US07617332B2
公开(公告)日：2009-11-10
申请号：US10427865
申请日：2003-05-01
摘要： A method, apparatus and computer program product are provided for implementing packet command instructions for network processing. A set of packet commands is provided. Each packet command defines a corresponding packet operation. A command from the set of packet commands is issued to perform the defined corresponding packet operation. A packet buffer structure hardware is provided for performing one or more predefined packet manipulation functions responsive to the issued command.
摘要翻译： 提供了一种用于实现用于网络处理的分组命令指令的方法，装置和计算机程序产品。 提供一组分组命令。 每个分组命令定义相应的分组操作。 发出来自该组命令的命令以执行定义的对应的分组操作。 提供了分组缓冲器结构硬件，用于响应于发出的命令执行一个或多个预定义的分组操纵功能。
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公开(公告)号：US08792332B2
公开(公告)日：2014-07-29
申请号：US12884389
申请日：2010-09-17
CPC分类号： H04L12/2602 , G06F11/0745 , G06F11/0793 , G06F13/4009 , H04L43/00 , H04W24/00 , H04W24/08 , H04W28/04
摘要： A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.
摘要翻译： 一种用于实现用于容错通信链路的车道混洗的方法和电路，以及设置有该主题电路所在的设计结构。 随机的硬件逻辑将一组虚拟数据通道引导到一组物理光学通道上，在链路初始化训练期间绕着被检测为坏的所有通道转向。 在链路训练期间，掩码状态寄存器加载了通道故障信息的掩码，标志着不良通道（如果有的话）。 洗牌硬件逻辑使用移位模板，其中起始模板中的每个位置都是表示对应车道位置的值。 移位模板通过由失败掩码控制的一组移位器进行级联。
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8.发明授权公开(公告)号：US07961732B2
公开(公告)日：2011-06-14
申请号：US12044998
申请日：2008-03-09
IPC分类号： H04L12/28 , G06F15/167 , G06F15/173
CPC分类号： H04L69/12
摘要： A method and apparatus are provided for implementing frame alteration commands in a communications network processor. A set of frame alteration instruction templates is defined. A frame alteration instruction template is identified based upon the packet type recognition result of a received packet. A frame alteration instruction stream is generated utilizing the frame alteration instruction template. Each of the frame alteration instruction templates includes different frame alteration commands to be performed on a packet. Pointers to indirect data bytes to be inserted in a packet are stored in the frame alteration instruction templates. The generated frame alteration instruction stream is used by hardware to provide frame alterations.
摘要翻译： 提供了一种用于在通信网络处理器中实现帧改变命令的方法和装置。 定义了一组帧改变指令模板。 基于接收到的分组的分组类型识别结果来识别帧改变指令模板。 使用帧改变指令模板生成帧改变指令流。 每个帧改变指令模板包括要在分组上执行的不同帧改变命令。 要插入数据包的间接数据字节的指针存储在帧改变指令模板中。 生成的帧改变指令流被硬件用于提供帧改变。
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9.发明授权Method for implementing actions based on packet classification and lookup results 有权基于分组分类和查找结果实现动作的方法公开(公告)号：US07382777B2
公开(公告)日：2008-06-03
申请号：US10463288
申请日：2003-06-17
IPC分类号： H04L12/56 , G06F12/00 , G06F15/173
CPC分类号： H04L47/10 , H04L47/2408 , H04L47/2441
摘要： A method and apparatus are provided for implementing predefined actions based upon packet classification and lookup results in a communications network processor. A plurality of sets of rules is defined. Each rule set includes at least one rule and each rule has a set of masked compares for comparing results of hits and misses of table lookups. Each masked compare set has an associated field for selecting an action. The action defines a set of one or more commands and each command defines a processing operation. One rule set is identified based upon the packet classification result for a received packet. When one of the rules is identified having a match of the masked compares, then the action of associated with the identified rule is selected. Otherwise a default action is provided responsive to no rule of the identified rule set having a match of the masked compares.
摘要翻译： 提供了一种基于通信网络处理器中的分组分类和查找结果来实现预定动作的方法和装置。 定义了多组规则。 每个规则集包括至少一个规则，每个规则具有一组掩码的比较，用于比较表查找的命中和未命中的结果。 每个被屏蔽的比较集合都有一个关联的字段用于选择一个动作。 该动作定义一组一个或多个命令，每个命令定义一个处理操作。 基于接收到的分组的分组分类结果来识别一个规则集。 当识别出其中一个规则具有被掩蔽的比较的匹配时，则选择与所识别的规则相关联的动作。 否则，响应于不具有所掩蔽的比较的匹配的所识别的规则集的规则来提供默认动作。
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公开(公告)号：US5751990A
公开(公告)日：1998-05-12
申请号：US233654
申请日：1994-04-26
CPC分类号： G06F12/1063
摘要： A hierarchical memory utilizes a translation lookaside buffer for rapid recovery of virtual to real address mappings and a cache system. Lines in the cache are identified in the cache directory by pointers to entries in the translation lookaside buffer. This eliminates redundant listings of the virtual and real addresses for the cache line from the cache directory allowing the directory to be small in size. Upon a memory access by a processing unit, a cache hash address is generated to access a translation lookaside buffer entry allowing comparison of the address stored in the TLB entry with the address of the memory access. Congruence implies a hit. Concurrently, the cache hash address indicates a pointer from the cache directory. The pointer should correspond to the cache hash address to indicate a cache directory hit. Where both occur a cache hit has occurred.
摘要翻译： 分层存储器利用翻译后备缓冲器来快速恢复虚拟到真实的地址映射和缓存系统。 缓存中的行通过指向转换后备缓冲区中的条目的缓存目录中标识。 这消除了缓存目录中虚拟和实际地址的高速缓存行的冗余清单，允许目录体积小。 在由处理单元进行存储器访问时，生成高速缓存散列地址以访问转换后备缓冲器条目，允许将存储在TLB条目中的地址与存储器访问的地址进行比较。 一致意味着一击。 同时，缓存散列地址指示缓存目录中的指针。 指针应对应于缓存哈希地址，以指示缓存目录命中。 发生高速缓存命中的地方。
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