发明申请
US20080191343A1 Integrated circuit package having large conductive area and method for fabricating the same
审中-公开
具有大导电面积的集成电路封装及其制造方法
- 专利标题: Integrated circuit package having large conductive area and method for fabricating the same
- 专利标题(中): 具有大导电面积的集成电路封装及其制造方法
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申请号: US11798159申请日: 2007-05-10
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公开(公告)号: US20080191343A1公开(公告)日: 2008-08-14
- 发明人: Chien-Hung Liu
- 申请人: Chien-Hung Liu
- 专利权人: XinTec Inc.
- 当前专利权人: XinTec Inc.
- 优先权: CN200710005733.4 20070213
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L21/98
摘要:
An integrated circuit package having large conductive area and method for fabricating the same is provided. The package includes an integrated circuit chip having upper and lower surfaces and a photosensitive device formed on the upper surface. A bonding pad is subsequently formed on the upper surface of the integrated circuit chip and electrically connected to the photosensitive device. A conductive layer is then formed on a sidewall of the integrated circuit chip and wrapped around an edge of the bonding pad to electrically connect to the bonding pad. In the package, the conductive layer is in contact with the upper and lower surfaces and a sidewall of the bonding pad. Because the conductive layer is wrapped around the edge of the bonding pad, contact surface and structural strength between the conductive layer and the bonding pad are increased.
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